MCZ33937AEK Freescale Semiconductor, MCZ33937AEK Datasheet - Page 27

• Manufacturer Part Number: MCZ33937AEK
• Description: IC PRE-DRIVER 3PH ENH 54-SOIC
• Manufacturer: Freescale Semiconductor
• Series: SMARTMOS™r
• Type: 3 Phase Pre-Driverr

Specifications of MCZ33937AEK

• Configuration: 3 Phase Bridge
• Input Type: Non-Inverting
• Delay Time: 265ns
• Current - Peak: 600mA
• Number Of Configurations: 1
• Number Of Outputs: 3
• High Side Voltage - Max (bootstrap): 15V
• Voltage - Supply: 8 V ~ 40 V
• Operating Temperature: -40°C ~ 135°C
• Mounting Type: Surface Mount
• Package / Case: 54-SOIC (7.5mm Width) Exposed Pad, 54-eSOIC, 54-HSOIC
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

five major functional blocks:
• Logic Inputs and Interface
• Bootstrap Supply
• Low Side Drivers
• High Side Drivers
• Charge Pump
LOGIC INPUTS AND INTERFACE
through timers.
hysteresis. Logic inputs are 3.0 V compatible. The logic
outputs are driven from the internal supply of approximately
5.0 V.
in the LOGIC COMMANDS AND REGISTERS section of this
document. SPI functionality includes the following:
• Programming of deadtime delay —This delay is
Analog Integrated Circuit Device Data
Freescale Semiconductor
All functions of the IC can be described as the following
This section contains the SPI port, control logic, and shoot-
The IC logic inputs have Schmitt trigger inputs with
The SPI registers and functionality is described completely
adjustable in approximately 50 ns steps from 0 ns to
MC33937 - Functional Block Diagram
Integrated Supply
Temperature
Current Sense
Phase Control
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
5V Regulator
Fault Register
Hold-off
Sensing & Protection
Integrated Supply
Figure 15. Functional Internal Block Description
Logic & Control
SPI Communication
Over-current
Sensing & Protection
Trickle Charge Pump
Under-voltage
VLS Regulator
Mode Control
Dead Time
De-sat
Phase
• Enabling of simultaneous operation of High Side and
• Setting of various operating modes of the IC and
• Read back of internal registers .
This means the leading edge on an input will cause the
12 µs. Calibration of the delay, because of internal IC
variations, is performed via the SPI.
Low Side FETs —Normally, both FETs would not be
enabled simultaneously. However, for certain applications
where the load is connected between the High Side and
Low Side FETs, this could be advantageous. If this mode
is enabled, the blanking time delay will be disabled. A
sequence of commands may be required to enable this
function to prevent inadvertent enabling. In addition, this
command can only be executed once after reset to enable
or disable simultaneous turn-on.
enabling of interrupt sources.
The 33937 allows different operating modes to be set and
locked by an SPI command (FULLON, Desaturation Fault,
Zero Deadtime). SPI commands can also determine how
the various faults are (or are not) reported.
The status of the 33937 Status Registers can be read back
by the Master (DSP or MCU).
The Px_HS and Px_LS logic inputs are edge sensitive.
Logic & Control
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
High Side
Pre-drivers
Low Side
Output
and
Drivers
33937
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