VND830SP STMicroelectronics, VND830SP Datasheet - Page 17

IC DRIVER DUAL 36V 6A POWERSO-10

VND830SP

Manufacturer Part Number
VND830SP
Description
IC DRIVER DUAL 36V 6A POWERSO-10
Manufacturer
STMicroelectronics
Type
High Sider
Datasheet

Specifications of VND830SP

Input Type
Non-Inverting
Number Of Outputs
2
On-state Resistance
60 mOhm
Current - Peak Output
9A
Voltage - Supply
5.5 V ~ 36 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
PowerSO-10 Exposed Bottom Pad
Supply Voltage (min)
5.5 V
Supply Current
40 mA
Maximum Power Dissipation
73500 mW
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output / Channel
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-2709-5

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VND830SP
3.1.2
3.2
3.3
Please note that, if the microprocessor ground is not shared by the device ground, then the
R
values. This shift will vary depending on how many devices are ON in the case of several
high-side drivers sharing the same R
If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.
Solution 2: a diode (D
A resistor (R
an inductive load. This small signal diode can be safely shared amongst several different
HSD. Also in this case, the presence of the ground network will produce a shift ( 600 mV) in
the input threshold and the status output values if the microprocessor ground is not common
with the device ground. This shift will not vary if more than one HSD shares the same
diode/resistor network. Series resistor in INPUT and STATUS lines are also required to
prevent that, during battery voltage transient, the current exceeds the Absolute Maximum
Rating. Safest configuration for unused INPUT and STATUS pin is to leave them
unconnected.
Load dump protection
D
V
line that are greater than those shown in the ISO T/R 7637/1 table.
MCU I/O protection
If a ground protection network is used and negative transients are present on the V
the control pins will be pulled negative. ST suggests to insert a resistor (R
prevent the microcontroller I/O pins from latching up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os:
Example
For the following conditions:
Recommended values are:
CC
GND
ld
is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
maximum DC rating. The same applies if the device is subject to transients on the V
- V
V
I
V
5 k
R
latchup
will produce a shift (I
CCpeak
OH C
prot
CCpeak
= 10 k
R
GND
= -100 V
prot
20 mA
4.5 V
/ I
latchup
= 1 k ) should be inserted in parallel to D
65 k .
R
prot
S(on)max
GND
Doc ID 7380 Rev 4
(V
) in the ground line
OH C
* R
GND
GND
- V
.
) in the input thresholds and the status output
IH
- V
GND
) / I
IHmax
GND
if the device will be driving
Application information
prot
) in line to
CC
line,
17/27
CC

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