BTS4160DGA Infineon Technologies, BTS4160DGA Datasheet - Page 18
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BTS4160DGA
Manufacturer Part Number
BTS4160DGA
Description
IC SWITCH PWR HISIDE DSO-14
Manufacturer
Infineon Technologies
Type
High Sider
Datasheet
1.BTS4160DGA.pdf
(26 pages)
Specifications of BTS4160DGA
Input Type
Non-Inverting
Number Of Outputs
2
On-state Resistance
160 mOhm
Current - Output / Channel
1.8A
Current - Peak Output
6.5A
Voltage - Supply
5.5 V ~ 20 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
DSO-14
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
BTS4160DGA
BTS4160DGATR
SP000360284
BTS4160DGATR
SP000360284
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
BTS4160DGA
Manufacturer:
INFINEON
Quantity:
1 683
Part Number:
BTS4160DGA
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
7
For diagnosis purpose, the BTS4160DGA provides a status pin per channel.
7.1
BTS4160DGA status pins are an open drain, active low circuit.
as no “hard” failure mode occurs (Short circuit to GND / Over temperature or open load in OFF), the signal is
permanently high, and due to a required external pull-up to the logic voltage will exhibit a logic high in the
application. A suggested value for the
.
Figure 12
7.2
Table 3
Table 3
Device operation
Normal operation
Open Load channel
Over temp channel
1)L if potential at the output exceeds the Openload detection voltage
7.2.1
For open load diagnosis in OFF-state, an external output pull-up resistor (
of the pull-up resistor value, the leakage currents and the open load threshold voltage
account.
I
leakages e.g. due to humidity, corrosion, etc... in the application.
To reduce the stand-by current of the system, an open load resistor switch
Data Sheet
leakage
defines the leakage current in the complete system, including
gives a quick reference for the logical state of the ST 0/1 pins during device operation.
Figure 13
Diagnostic Mechanism
ST 0/1 Pin
Status output circuitry
ST0/1 Signal in Case of Failures
ST Pin truth table
Diagnostic in Open Load, Channel OFF
gives a sketch of the situation and
Channel 0
Diagnostic
Logic
R
PU ST01
is 15k
GND
Figure 14
IN
L
H
L
H
L
H
18
ZD
ST
ESD
ST pin full diag.vsd
Figure 12
shows the typical timing diagram.
R
PU ST
V
I
ccµC
L(OFF)
shows the equivalent circuitry. As long
R
OUT
L
H
> V
H
L
L
S
OL
OL
R
(OL)
) is recommended. For calculation
ST
is recommended.
(see
V
Chapter
OL(OFF)
Diagnostic Mechanism
Rev. 1.0, 2008-03-18
has to be taken into
ST
H
H
L
H
H
L
5.4) and external
BTS4160DGA
1)