MC33931VWR2 Freescale Semiconductor, MC33931VWR2 Datasheet - Page 3

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MC33931VWR2

Manufacturer Part Number
MC33931VWR2
Description
IC H-BRIDGE THROTTLE CTRL 44HSOP
Manufacturer
Freescale Semiconductor
Type
H Bridger
Datasheet

Specifications of MC33931VWR2

Input Type
Non-Inverting
Number Of Outputs
2
On-state Resistance
120 mOhm
Current - Output / Channel
5A
Current - Peak Output
11A
Voltage - Supply
8 V ~ 28 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
44-HSOP
Product
H-Bridge Drivers
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 1. 33931 Pin Definitions
Analog Integrated Circuit Device Data
Freescale Semiconductor
A functional description of each pin can be found in the Functional Description section beginning on
10,11,34,35
4-6,40,39
36-38
Pin
7-9
1
2
3
Pin Name
EN/D2
VPWR
PGND
OUT1
OUT2
D1
FB
Power Input
Logic Input
Logic Input
Function
Ground
Analog
Output
Output
Output
Power
Power
Power
Pin
EN/D2
VPWR
VPWR
VPWR
PGND
PGND
OUT1
OUT1
OUT1
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
D1
FB
H-bridge Output 1
H-bridge Output 2
Disable Input 1
Positive Power
Power Ground
Formal Name
(Active High)
Enable Input
Feedback
Supply
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Figure 3. 33931 Pin Connections
PIN CONNECTIONS
When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated. Schmitt trigger
input with ~80 μA source so default condition = disabled.
The load current feedback output provides ground referenced 0.24% of the high
side output current. (Tie to GND through a resistor if not used.)
When EN/D2 is logic HIGH the H-bridge is operational. When EN/D2 is logic
LOW, the H-bridge outputs are tri-stated and placed in Sleep mode. (logic input
with ~ 80 μA sink so default condition = Sleep mode.)
These pins must be connected together physically as close as possible and
directly soldered down to a wide, thick, low resistance supply plane on the PCB.
Source of high side MOSFET1 and drain of low side MOSFET1.
High-current power ground pins must be connected together physically as
close as possible and directly soldered down to a wide, thick, low resistance
ground plane on the PCB.
Source of high side MOSFET2 and drain of low side MOSFET2.
AGND
Tab
Tab
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Definition
SF
IN1
IN2
CCP
VPWR
VPWR
OUT2
OUT2
OUT2
PGND
PGND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
page
11.
PIN CONNECTIONS
33931
3

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