MC33984BPNAR2 Freescale Semiconductor, MC33984BPNAR2 Datasheet - Page 34

• Manufacturer Part Number: MC33984BPNAR2
• Description: IC SWITCH HI SIDE DUAL 16-PQFN
• Manufacturer: Freescale Semiconductor
• Type: High Sider

Specifications of MC33984BPNAR2

• Input Type: SPI
• Number Of Outputs: 2
• On-state Resistance: 4 mOhm
• Voltage - Supply: 6 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-PQFN, 16-PowerQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output / Channel: -
• Current - Peak Output: -

ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Introduction
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
Packaging and Thermal Considerations
independently heating with P
T
temperature while only heat source 1 is heating with P
reference temperature while heat source 2 is heating with P
and R
This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated
values were obtained by measurement and simulation according to the standards listed below.
Standards
Table 1. Thermal Performance Comparison
34
33984
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Notes:
J1
This thermal addendum is provided as a supplement to the 33984 technical
This package is a dual die package. There are two heat sources in the package
For m, n = 1, R
For m = 1, n = 2, R
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
R
R
R
R
1.
2.
3.
4.
5.
and T
Resistance
θJAmn
θJBmn
θJAmn
θJCmn
Thermal
θJ22
Per JEDEC JESD51-2 at natural convection, still air
condition.
2s2p thermal test board per JEDEC JESD51-7 and
JESD51-5.
Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
Thermal resistance between the die junction and the
exposed pad; “infinite” heat sink attached to exposed pad.
J2
, respectively.
(2) (3)
(1) (4)
(1) (2)
(5)
, and a thermal resistance matrix with R
θJA11
θJA12
1 = Power Chip, 2 = Logic Chip [°C/W]
m = 1,
n = 1
<0.5
is the thermal resistance from Junction 1 to the reference
6.0
T
T
20
53
J1
J2
is the thermal resistance from Junction 1 to the
1
=
and P
R
R
m = 1, n = 2
m = 2, n = 1
θJA11
θJA21
2
. This results in two junction temperatures,
2.0
0.0
16
40
R
R
θJA12
θJA22
θJAmn
.
m = 2,
n = 2
1.0
39
26
72
1
P
P
.
1
2
.
2
. This applies to R
Note: Recommended via diameter is 0.5 mm. PTH (plated through
hole) via must be plugged / filled with epoxy or solder mask in order
to minimize void formation and to avoid any solder wicking into the
via.
Figure 1. Surface Mount for Power PQFN
θJ21
Note For package dimensions, refer to
the 33984 data sheet.
with Exposed Pads
Analog Integrated Circuit Device Data
HIGH SIDE SWITCH
12 mm x 12 mm
98ARL10521D
16-PIN PQFN
PNA SUFFIX
33984
Freescale Semiconductor
* All measurements
0.2
are in millimeters
1.0
0.2
1.0