ISL6580CR Intersil, ISL6580CR Datasheet - Page 13

• Manufacturer Part Number: ISL6580CR
• Description: IC DRIVER HIGH SIDE FET 56-QFN
• Manufacturer: Intersil
• Type: High Side/Low Side Driverr

Specifications of ISL6580CR

• Input Type: Non-Inverting
• Number Of Outputs: 12
• On-state Resistance: 20 mOhm
• Current - Output / Channel: 25A
• Current - Peak Output: 35A
• Voltage - Supply: 5 V ~ 12 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

A sample of the peak current through the MOSFET is taken
each clock cycle, converted to a digital signal, and sent to
the controller. The master oscillator frequency inside the
Intersil Digital Architecture is 133.33MHz. Figure 9 shows
the voltage drop across the sense resistor, the voltage at the
switch node, the inductor current, and the digital voltage
signal. The inductor current signal is delayed slightly due to
the probe parasitics. As can be seen from the figure, 13nS
prior to the turn off of the high side MOSFET a sample of the
voltage across the sense resistor is taken (I
done to avoid voltage spiking during the switching of the
node. After sampling, I
(I
pin.
DIG
FIGURE 8. INTERNAL STRUCTURE OF THE ISL6580 POWER
FIGURE 9. VOLTAGE DROP ACROSS THE SENSE
). The controller receives the digital signal from the I
STAGE
RESISTOR, VOLTAGE AT SWITCH NODE,
INDUCTOR CURRENT, AND DIGITAL VOLTAGE
SIGNAL
SENSE
13
is converted to a digital signal
SENSE
). This is
DIG
ISL6580
Current Sharing
Each ISL6580 senses current in it’s upper MOSFET as
described above and converts it to a serial digital signal on
the IDIGn lines. The sampled, digitized current, IDIG
each active channel is used to gauge both overall load
current and the relative channel current carried in each leg of
the converter. The individual sample currents are summed
and divided by the number of active channels. The resulting
average current, I
current demand on the converter and the appropriate level of
channel current. The average current is then subtracted from
the individual channel sample currents. The resulting error
current, I
modified V
signal and produces a pulse width which corrects for any
unbalance and drives the error current toward zero.
Loop Compensation
Any closed loop system must be designed to insure stability
(prevent oscillation) and provide correct response to external
events such as load transients. The output of a buck
regulator has an inherent, low pass filter formed by the
output inductor(s), output capacitance and their ESRs
(Equivalent Series Resistance). Figure 1 shows a typical
gain and phase plot of output inductors, capacitors and ESR.
IDIGn
IDIG1
FIGURE 11. FREQUENCY RESPONSE OF THE OUTPUT
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
1
ER
COMP
, is then filtered before it adjusts V
INDUCTORS AND CAPACITORS
FIGURE 10. CURRENT BALANCE
+
+
Σ
Kav
10
signal is compared to a sawtooth ramp
AVG
-
CURRENT BALANCE
+
Σ
, provides a measure of the total load
Frequency (in KHz)
+
+
Σ
100
z
-1
Kiav
Plant Gain
Phase
1000
+
+
Σ
COMP
GENERATE
BLOCK
10000
PWM n
. The
n
, from
0
-20
-40
-60
-80
-100
-120
-140