AMIS30512C5122RG ON Semiconductor, AMIS30512C5122RG Datasheet - Page 23

• Manufacturer Part Number: AMIS30512C5122RG
• Description: IC MOTOR DVR MICRO STEP 24SOIC
• Manufacturer: ON Semiconductor

Specifications of AMIS30512C5122RG

• Applications: Stepper Motor Driver, 2 Phase
• Number Of Outputs: 1
• Current - Output: 800mA
• Voltage - Supply: 6 V ~ 30 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Examples of Combined READ and WRITE Operations
operations are combined. In Figure 17 the Master first reads
the status from Register at ADDR4 and at ADDR5 followed
back command in order to verify the data correctly written
as illustrated in Figure 18. During reception of the READ
command the old data is returned for a second time. Only
after receiving the READ command the new data is
NOTE:
DATA from previous command or
NOT VALID after POR or RESET
Data from previous com-
mand or NOT VALID after
POR or RESET
In the following examples successive READ and WRITE
After the write operation the Master could initiate a read
DATA from previous command or
NOT VALID after POR or RESET
Figure 19. Single WRITE Operation where DATA from the Master is Written in SPI Register with Address 3
Registers are updated with the internal
status at the rising edge of CS
CS
Figure 21. A WRITE Operation where DATA from the Master is Written in SPI Register with Address 2
DO
DI
The internal data−out shift buffer of AMIS−30512 is updated with the content of the selected SPI register only at the last (every
eight) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be
written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.
DO
CS
DI
Registers are updated with the internal status at the rising
edge of the internal AMIS−30512 clock when CS = 1
DO
CS
DI
Followed by a READ Back Operation to Confirm a Correct WRITE Operation
Figure 20. 2 Successive READ Commands Followed by a WRITE Command
or NOT VALID
WRITE
OLD DATA
COMMAND
to ADDR2
DATA
or NOT VALID
READ
from ADDR4
COMMAND
OLD DATA
DATA
DATA
OLD DATA or NOT VALID
WRITE DATA to ADDR3
DATA
COMMAND
DATA
from ADDR2
NEW
OLD DATA
for ADDR2
DATA
DATA
http://onsemi.com
The NEW DATA is written into the corresponding
DATA
from ADDR5
from ADDR4
READ
COMMAND
DATA
DATA
DATA
23
internal register at the rising edge of CS
Registers are updated with the internal status at the rising
edge of the internal AMIS−30512 clock when CS = 1
by writing a control byte in Control Register at ADDR2.
Note that during the write command (in Figure 3) the old
data of the pointed register is returned at the moment the new
data is shifted in:
transmitted. This rule also applies when the master device
wants to initiate an SPI transfer to read the Status Registers.
Because the internal system clock updates the Status
Registers only when CSB line is high, the first read out byte
might represent old status information.
OLD DATA from ADDR3
READ
from ADDR2
from ADDR2
NEW DATA for ADDR3
COMMAND
OLD DATA
The NEW DATA is written into the corresponding
DATA
DATA to ADDR2
DATA
from ADDR5
DATA
DATA
COMMAND
WRITE
DATA
DATA
internal register at the rising edge of CS
from ADDR2
COMMAND
NEW DATA
or DUMMY
DATA
from ADDR2
NEW DATA
OLD DATA
for ADDR2
DATA
DATA