AMIS30512C5122RG ON Semiconductor, AMIS30512C5122RG Datasheet - Page 24

• Manufacturer Part Number: AMIS30512C5122RG
• Description: IC MOTOR DVR MICRO STEP 24SOIC
• Manufacturer: ON Semiconductor

Specifications of AMIS30512C5122RG

• Applications: Stepper Motor Driver, 2 Phase
• Number Of Outputs: 1
• Current - Output: 800mA
• Voltage - Supply: 6 V ~ 30 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SPI Control Registers
Where:
Where:
Where:
Table 12. SPI Control Register WR
Table 13. SPI Control Register 0
Table 14. SPI Control Register 1
Address
Address
Address
All SPI control registers have Read/Write access and default to “0” after power−on or hard reset.
R/W
Reset:
WDEN:
WDT[3:0]:
R/W
Reset:
SM[2:0]:
CUR[4:0]:
R/W
Reset:
DIRCTRL
NXTP
PWMF
PWMJ
EMC[1:0]
00h
01h
02h
Access
Reset
Data
Access
Reset
Data
Content
Content
Content
Access
Reset
Data
Read and Write access
Status after power-On or hard reset
Watchdog enable. Writing “1” to this bit will activate the watchdog timer (if not enabled yet) or will clear
this timer (if already enabled). Writing “0” to this bit will clear WD bit (SPI Status Register 0).
Watchdog timeout interval
Read and Write access
Status after power−On or hard reset
Step mode
Current amplitude
Read and Write access
Status after power−on or hard reset
Direction control
NEXT polarity
PWM frequency
PWM jitter
EMC slope control
DIRCTRL
WDEN
Bit 7
R/W
Bit 7
Bit 7
R/W
R/W
0
0
0
SM[2:0]
NXTP
Bit 6
Bit 6
Bit 6
R/W
R/W
R/W
0
0
0
Control Register 0 (CR0)
Control Register 1 (CR1)
Control Register (WR)
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Bit 5
Bit 5
Bit 5
R/W
R/W
R/W
0
0
0
−
WDT[3:0]
24
Bit 4
Bit 4
Bit 4
R/W
R/W
R/W
0
0
0
−
Structure
Structure
Structure
PWMF
Bit 3
Bit 3
Bit 3
R/W
R/W
R/W
0
0
0
CUR[4:0]
PWMJ
Bit 2
Bit 2
Bit 2
R/W
R/W
R/W
0
−
0
0
Bit 1
Bit 1
Bit 1
R/W
R/W
R/W
0
−
0
0
EMC[1:0]
Bit 0
Bit 0
Bit 0
R/W
R/W
R/W
0
−
0
0