IR3510MTRPBF International Rectifier, IR3510MTRPBF Datasheet - Page 21

• Manufacturer Part Number: IR3510MTRPBF
• Description: IC XPHASE CONTROL 32-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase™r

Specifications of IR3510MTRPBF

• Applications: Processor
• Mounting Type: Surface Mount
• Package / Case: 32-MLPQ
• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: IR3510MTRPBFTR

Input current limit
Input current limit is required for hot-swap application to eliminate the inrush current drawn from the VIN power
supply. There are two stages of input current limit. The first stage is input current limit, in which the input FET runs
into linear mode first to limit the input current, and it is then latched off after a programmable delay time. The second
stage is the severe over current protection. The input FET is immediately turned off once the input current reaches
the severe OCP threshold. Since it is not latched, once the current is reduced below the severe OCP threshold, the
input FET runs into normal current limit mode and then latched off after time-out.
The input current is sensed by a sense resistor placed
after and in series with the input FET. A 20uA current
source going out of the “ICS-“ pin flows through
Rocset and sets the input current limit threshold.
Iocset = Rocset x 20uA / Rs
The severe OCP threshold voltage is 60mv above the
normal current limit threshold, which gives,
Isevere = (Rocset x 20uA + 60mv) / Rs
The input OCP delay is set by an external cap
connected on the “IOCD” pin. Once the input current
limit threshold is reached, a 20uA current source going
out of the “IOCD” pin charges the Cocd. The input FET
is turned off once the “IOCD” is charged above 0.8V
threshold voltage. The time-out delay is,
Tocd = Cocd x 0.8V / 20uA
Two-Level Enable Threshold Voltages
The IR3510 is designed for multiple outputs application, in which a common input FET is used. In order to turn on
each output independently, two-level Enable threshold voltages are used. The first threshold voltage is 0.7v, and is
used to turn on just the input FET; The second threshold is 1.2v, and is used to turn on the voltage regulator output.
The “Enable” pin has internal pull-up to 0.9V. If it is left open, it is above the first threshold, so it turns on the input
FET. To turn on the voltage regulator output, a voltage higher than the second threshold voltage needs to be
applied to the “Enable” pin.
Two-Stage Soft-Start
The IR3510 has a two-stage programmable soft-start to limit the surge current during both the input FET turn-on
and the voltage regulator start-up. The soft-start capacitor connected between the “SS” and “LGND” pins controls
soft start timing. A charge current of 70uA control the up slope of the voltage at the “SS” pin.
The first stage soft-start is controlled by the first enable threshold voltage. Once the Enable voltage is above its first
threshold, the soft-start cap is charged up until it reaches its charge-up threshold voltage. During this soft-start time,
the input FET is controlled by the input soft-start regulator and the voltage after the input FET ramps up following
the soft-start cap voltage. If the Enable voltage is below the second enable threshold voltage, the SS voltage will be
kept charged and complete the soft-start of the input FET.
If a voltage higher than the second enable threshold is applied to the Enable pin after the input FET is fully turned
on, the soft-start cap is quickly discharged and then re-charged up by the same 70ua charging current to provide
the soft-start for the voltage regulator output.
Page 21 of 36
IR Confidential
VIN
GATE_I
VCX
IOCD
Cocd
Fig. 8 Input OCP Control
20uA
OC REGULATOR
Time-out
Latch
+
-
May 18, 2009
Rs
Rocset
SEVERE OC COMPARATOR
IR3510
+
-
20uA
3K
ICS+
ICS-
P12V