CP82C88 Intersil, CP82C88 Datasheet
CP82C88
Specifications of CP82C88
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CP82C88 Summary of contents
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... M82C88 . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C 16 DEN • Pb-Free Plus Anneal Available (RoHS Compliant) 15 CEN Ordering Information 14 INTA 13 IORC PART NUMBER 12 AIOWC CP82C88 11 IOWC CP82C88Z (Note) CP82C88-10 CP82C88- PDIP IP82C88 CS82C88 IS82C88 18 S2 CD82C88 17 MCE/PDEN ID82C88 16 DEN MD82C88/B 8406901RA 15 CEN MR82C88/B 14 INTA 84069012A NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets ...
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Functional Diagram CLK AEN CONTROL INPUT CEN IOB Pin Description PIN SYMBOL NUMBER TYPE The +5V power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for decoupling ...
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Pin Description (Continued) PIN SYMBOL NUMBER TYPE AMWC 8 O ADVANCED MEMORY WRITE COMMAND: The AMWC issues a memory write command earlier in the machine cycle to give memory devices an early indication of a write instruction. Its timing is ...
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Control Outputs The control outputs of the 82C88 are Data Enable (DEN), Data Transmit/Receive (DT/R) and Master Cascade Enable/ Peripheral Data Enable (MCE/PDEN). The DEN signal determines when the external bus should be enabled onto the local bus and the ...
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Absolute Maximum Ratings Supply Voltage ...
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AC Electrical Specifications PARAMETER SYMBOL TIMING REQUIREMENTS (1) TCLCL CLK Cycle Period (2) TCLCH CLK Low Time (3) TCHCL CLK High Time (4) TSVCH Status Active Setup Time (5) TCHSV Status Inactive ...
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AC Testing Input, Output Waveform INPUT V +0.4V IH 1.5V V -0.4V IL A.C. Testing: All input signals (other than CLK) must switch between V -0.4V and V +0.4. CLK must switch between 0. and V -0.4V. Input ...
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Timing Waveforms (Note 3) T STATE 4 CLK TCHSV (5) S2, S1, S0 ADDRESS/DATA TCLLH (10) ALE MRDC, IORC, INTA, AMWC, AIOWC MWTC, IOWC DEN (READ) (INTA) PDEN (READ) (INTA) DEN (WRITE) PDEN (WRITE) TCHDTH (18) DT/R (READ) (INTA) MCE ...
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Timing Waveforms (Note 3) (Continued) CEN AEN DEN PDEN AEN TAELCH (19) OUTPUT COMMAND CEN CEN MUST BE LOW OR INVALID PRIOR PREVENT THE COMMAND FROM BEING GENERATED. FIGURE 3. ADDRESS ENABLE (AEN) TIMING (THREE-STATE ENABLE/DISABLE) NOTES: ...
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Burn-In Circuits NOTES: = 5.5V ± 0.5V ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...