LTC1966CMS8 Linear Technology, LTC1966CMS8 Datasheet - Page 17

IC PREC RMS/DC CONV MCRPWR 8MSOP

LTC1966CMS8

Manufacturer Part Number
LTC1966CMS8
Description
IC PREC RMS/DC CONV MCRPWR 8MSOP
Manufacturer
Linear Technology
Datasheet

Specifications of LTC1966CMS8

Current - Supply
155µA
Voltage - Supply
2.7 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
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APPLICATIO S I FOR ATIO
prior generation log/antilog RMS-to-DC converters, whose
averaging time constants are dependent on the signal
level, resulting in excruciatingly long waits for the output
to go to zero.
The shape of the rising and falling edges will be dependent
on the total percent change in the step, but for less than the
100% changes shown in Figure 11, the responses will be
less distorted and more like a standard exponential decay.
For example, when the input amplitude is changed from
100mV to 110mV (+10%) and back (–10%), the step
responses are essentially the same as a standard expo-
nential rise and decay between those two levels. In such
cases, the time constant of the decay will be in between
that of the rising edge and falling edge cases of Figure 11.
Therefore, the worst case is the falling edge response as
it goes to zero, and it can be used as a design guide.
0.1
10
1
0.01
Figure 11a. LTC1966 Rising Edge with C
120
100
80
60
40
20
0
0
C
AVE
= 1 F
0.1
U
C = 0.1 F
0.2
TIME (SEC)
U
0.3
C = 0.22 F
0.1
Figure 12. LTC1966 Settling Time with One Cap Averaging
W
0.4
1966 F11a
C = 0.47 F
AVE
0.5
= 1 F
U
C = 1 F
SETTLING TIME (SEC)
C = 2.2 F
1
Figure 12 shows the settling accuracy vs settling time for
a variety of averaging capacitor values. If the capacitor
value previously selected (based on error requirements)
gives an acceptable settling time, your design is done.
But with 100 F, the settling time to even 10% is a full 38
seconds, which is a long time to wait. What can be done
about such a design? If the reason for choosing 100 F is
to keep the DC error with a 75mHz input less than 0.1%,
the answer is: not much. The settling time to 1% of 76
seconds is just 5.7 cycles of this extremely low frequency.
Averaging very low frequency signals takes a long time.
However, if the reason for choosing 100 F is to keep the
peak error with a 10Hz input less than 0.05%, there is
another way to achieve that result with a much improved
settling time.
Figure 11b. LTC1966 Falling Edge with C
C = 4.7 F
120
100
80
60
40
20
0
0
C
AVE
C = 10 F
= 1 F
0.2
0.4
TIME (SEC)
C = 22 F
10
0.6
C = 47 F
0.8
1966 F11b
LTC1966
AVE
1
C = 100 F
= 1 F
sn1966 1966fas
17
1966 F12
100

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