LTC1966IMS8 Linear Technology, LTC1966IMS8 Datasheet - Page 16

• Manufacturer Part Number: LTC1966IMS8
• Description: IC PREC RMS/DC CONV MCRPWR 8MSOP
• Manufacturer: Linear Technology

Specifications of LTC1966IMS8

• Current - Supply: 155µA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC1966
In any configuration, the averaging capacitor should be
connected between Pins 5 and 6. The LTC1966 RMS-DC
output will be a positive voltage created at V
with respect to OUT RTN (Pin 6).
Power Supply Bypassing
The LTC1966 is a switched capacitor device, and large
transient power supply currents will be drawn as the
switching occurs. For reliable operation, standard power
supply bypassing must be included. For single supply
operation, a 0.01 F capacitor from V
(Pin 1) located close to the device will suffice. For dual
supplies, add a second 0.01 F capacitor from V
to GND (Pin 1), located close to the device. If there is a
good quality ground plane available, the capacitors can go
directly to that instead. Power supply bypass capacitors
can, of course, be inexpensive ceramic types.
The LTC1966 needs at least 2.7V for its power supply,
more for dual supply configurations. The range of allow-
able negative supply voltages (V
voltages (V
V
The LTC1966 has internal ESD absorption devices, which
are referenced to the V
in-circuit ESD immunity, the V
connected to a low external impedance. This can be
accomplished with low impedance power planes or simply
with the recommended 0.01 F decoupling to ground on
each supply.
16
SS
– 3 • (V
constraint is:
DD
–5
–6
–1
–2
–3
–4
DD
0
2.5
– 2.7V) V
) is shown in Figure 10. Mathematically, the
Figure 10. V
3
U
3.5
DD
OPERATES IN THIS RANGE
SS
U
V
and V
DD
SS
4
(V)
Limits vs V
GND
LTC1966
DD
SS
4.5
SS
and V
supplies. For effective
W
) vs positive supply
DD
5
DD
1966 F10
SS
(Pin 7) to GND
5.5
pins must be
OUT
U
SS
(Pin 5)
(Pin 4)
3
100mV. At very low frequencies, the LTC1966 will essentially track the input. But as the input
frequency is increased, the average result will converge to the RMS value of the input. If the rise and
fall characteristics were symmetrical, the output would converge to 50mV. In fact though, the RMS
value of a 100mV DC-coupled 50% duty cycle pulse train is 70.71mV, which the asymmetrical rise
and fall characteristics will converge to as the input frequency is increased.
Up and Running!
If you have followed along this far, you should have the
LTC1966 up and running by now! Don’t forget to enable
the device by grounding Pin 8, or driving it with a logic low.
Keep in mind that the LTC1966 output impedance is fairly
high, and that even the standard 10M input impedance
of a digital multimeter (DMM) or a 10 scope probe will load
down the output enough to degrade its typical gain error
of 0.1%. In the end application circuit, either a buffer or
another component with an extremely high input imped-
ance (such as a dual slope integrating ADC) should be used.
For laboratory evaluation, it may suffice to use a bench-top
DMM with the ability to disconnect the 10M shunt.
If you are still having trouble, it may be helpful to skip
ahead a few pages and review the Troubleshooting Guide.
What About Response Time?
With a large value averaging capacitor, the LTC1966 can
easily perform RMS-to-DC conversion on low frequency
signals. It compares quite favorably in this regard to prior-
generation products because nothing about the
circuitry is temperature sensitive. So the RMS result
doesn’t get distorted by signal driven thermal fluctuations
like a log-antilog circuit output does.
However, using large value capacitors results in a slow
response time. Figure 11 shows the rising and falling step
responses with a 1 F averaging capacitor. Although they
both appear at first glance to be standard exponential-
decay type settling, they are not. This is due to the
nonlinear nature of an RMS-to-DC calculation. Also note
the change in the time scale between the two; the rising
edge is more than twice as fast to settle to a given
accuracy. Again this is a necessary consequence of RMS-
to-DC calculation.
Although shown with a step change between 0mV and
100mV, the same response shapes will occur with the
LTC1966 for ANY step size. This is in marked contrast to
To convince oneself of this necessity, consider a pulse train of 50% duty cycle between 0mV and
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