LM81CIMT-3/NOPB National Semiconductor, LM81CIMT-3/NOPB Datasheet - Page 28

• Manufacturer Part Number: LM81CIMT-3/NOPB
• Description: IC MONITOR SYS HARDWAR 24-TSSOP
• Manufacturer: National Semiconductor

Specifications of LM81CIMT-3/NOPB

• Function: Hardware Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Speed Control, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: No
• Voltage - Supply: 2.8 V ~ 3.8 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Supply Voltage Range: 2.8V To 3.8V
• Reset Type: Active-Low
• Supply Current: 1.4mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 24
• Operating Temperature Range: -40°C To +125°C
• Rohs Compliant: Yes
• Monitored Voltage: 2.5 V , 3.3 V , 5 V , 12 V
• Manual Reset: Not Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No
• Supply Voltage (max): 3.8 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 400 uA (Typ)
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM81CIMT-3; *LM81CIMT-3/NOPB; LM81CIMT-3

www.national.com
0-6
Bit
Bit
0
1
2
3
4
5
6
7
7
Functional Description
13.7 Interrupt Mask Register 2 — Address 44h
Power on default –
13.8 Reserved Register — Address 45h
Power on default –
13.9 CI Clear Register — Address 46h
Power on default –
+12Vin
Vccp2
Reserved
Reserved
Chassis Intrusion
Reserved
Reserved
RESET Enable
Reserved
CI Clear
Name
Name
<
<
<
7:0
7:0
7:0
>
>
>
= 0000 0000 binary
= 00h. Read/Write for backwards compatibility.
= 0000 0000 binary
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/
Read/
Write
Write
(Continued)
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
A one outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. The
register bit self clears after the pulse has been output. This bit is mirrored in
Configuration Register bit 6.
<
7
>
= 1 in INT Mask Register 2 enables the RESET in the Configuration Register.
28
Description
Description