W83792G Nuvoton Technology Corporation of America, W83792G Datasheet - Page 51
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W83792G
Manufacturer Part Number
W83792G
Description
IC MONITOR H/W 48-LQFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheet
1.W83792AG.pdf
(97 pages)
Specifications of W83792G
Function
Hardware Monitor
Topology
ADC, Fan Control, Register Bank
Sensor Type
External
Sensing Temperature
External Sensor
Output Type
I²C™
Output Alarm
Yes
Output Fan
Yes
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
W83792G
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Company:
Part Number:
W83792GЈ¬ CЈ¬ 1E
Manufacturer:
Winbond
Quantity:
1 000
Reset Condition: Resume Reset, INIT, 5VDD posedge
W83792D supports different FAN power on time. The FAN will power on one by one after 5VDD is
ready. (At sequence FAN6-2-3-1-4-5) Fan Divisor also determines the FAN power on time. Under
power-on-default setting(divisor = 2), to power on all FAN will take 71.5ms. If divisor is change, the
timing will be different.
CR9E
8.18 VBAT Monitor Control Register -- Index 5Dh (Bank 0)
Reset Condition: Resume Reset
.
7,3
6-4,
2-0
BIT
7
6
5
VBAT Monitor Control
BIT
Mask
OLARIT
Manual
Trigger
FAN 7 Divisor and Control
NAME
FAN_OB
FAN_DIV
NAME
R/W
R/W
R/W
ATTRIBUTE
BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4
0
ATTRIBUTE
R/W
R/W
5D
RW
Fan7 Automatic/Manual Mode Selection. Clear to 0, always
polling FAN7 automatically; Set to 1, only polling once while
Trigger<bit 6> is set to 1.
Fan7 count trigger. Once set, W83792D will count FANIN7 in
Auto Mode.
After FAN count write back, this bit will be clear to 0.
Interrupt/SMI mask for FAN7.
FAN PWM Input Divisor.
000 - divided by 1;
001 - divided by 2(Default);
010 - divided by 4;
011 - divided by 8;
100 - divided by 16;
101 - divided by 32;
110 - divided by 64;
111 - divided by 128.
Enable Fan as Output Buffer. Set to 1, FANOUT can drive
logical high or logical low.
TT1
RO
TT2
RO
- 45 -
reserve
0
DESCRIPTION
DESCRIPTION
Publication Release Date: April 26, 2006
CLR_TT1
W83792AD/AG/D/G
BIT 3
0
CLR_TT2 reserve EN_VBAT
BIT 2
0
BIT 1
0
Revision 0.9
BIT 0
0