W83792G Nuvoton Technology Corporation of America, W83792G Datasheet - Page 57
W83792G
Manufacturer Part Number
W83792G
Description
IC MONITOR H/W 48-LQFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheet
1.W83792AG.pdf
(97 pages)
Specifications of W83792G
Function
Hardware Monitor
Topology
ADC, Fan Control, Register Bank
Sensor Type
External
Sensing Temperature
External Sensor
Output Type
I²C™
Output Alarm
Yes
Output Fan
Yes
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
W83792G
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Company:
Part Number:
W83792GЈ¬ CЈ¬ 1E
Manufacturer:
Winbond
Quantity:
1 000
8.24 Fan Stop/Start Duty Cycle/DC Level Registers -- Index 88h 89h 98h(Bank 0)
Reset Condition: Resume Reset, INIT, 5VDD posedge.
8.25 Fan Stop Time Register -- Index 8Ch 8Dh 9Ah(Bank 0)
Reset Condition: Resume Reset, INIT, 5VDD posedge.
BIT
7-4
3-0
BIT
7-0
FAN 1 Stop Time
FAN 2 Stop Time
FAN 3 Stop Time
FAN 1 Nonstop/Start
FAN 2 Nonstop/Start
FAN 3 Nonstop/Start
MNEMONIC
MNEMONIC
STOP_TIME
START_DC
STOP_DC
NAME
NAME
R/W
R/W
ATTRIBUTE
BANK
R/W
ATTRIBUTE
0
0
0
BANK
0
0
0
INDEX
8C
8D
9A
INDEX
88
89
98
In Thermal Cruise mode, PWM duty will increase from 0 to this
register value to provide a minimum duty cycle to turn on the
fan. This register should be written a fan start-up duty cycle.
At Smart Fan II mode. This register is used as Fan Duty Cycle
Level 1.
In Thermal Cruise mode, PWM duty will be 0 if it decreases to
under this value. This register should be written a non-zero
minimum PWM stop duty cycle.
In Thermal Cruise mode, this register determines the time of
which PWM duty/DC Level is from stop duty cycle/DC level to
0. The unit of this register is 0.1 second. Set Stop Time to 0
implies never stop FANs. The default value is 6 seconds.
ATTR
RW
RW
RW
ATTR
RW
RW
RW
BIT 7
BIT 7
- 51 -
BIT 6
BIT 6
START_DC1
START_DC2
START_DC3
01h
01h
01h
BIT 5
DESCRIPTION
BIT 5
DESCRIPTION
Publication Release Date: April 26, 2006
W83792AD/AG/D/G
STOP_TIME1
STOP_TIME2
STOP_TIME3
BIT 4
3Ch (6 sec)
3Ch (6 sec)
3Ch (6 sec)
BIT 4
BIT 3
BIT 3
MIN_NOSTOP_DC1
MIN_NOSTOP_DC2
MIN_NOSTOP_DC3
BIT 2
BIT 2
01h
01h
01h
BIT 1
BIT 1
Revision 0.9
BIT 0
BIT 0