ADT7490ARQZ-REEL ON Semiconductor, ADT7490ARQZ-REEL Datasheet
ADT7490ARQZ-REEL
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ADT7490ARQZ-REEL Summary of contents
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ADT7490 R dBCool Remote Thermal Monitor and Fan Controller with PECI Interface The ADT7490 is a dBCool thermal monitor and multiple PWM fan controller for noise−sensitive or power−sensitive applications requiring active system cooling. The ADT7490 includes a local temperature sensor, ...
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GPIO1 GPIO REGISTER GPIO2 PERFORMANCE THERM/ MONITORING SMBALERT THERMAL PROTECTION TACH1 FAN TACH2 SPEED TACH3 COUNTER TACH4 PWM PWM1 REGISTERS AND ACOUSTIC PWM2 CONTROLLERS ENHANCEMENT PWM3 (HF AND LF) PECI PECI INTERFACE CCP +12V IN ...
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ABSOLUTE MAXIMUM RATINGS Parameter Positive Supply Voltage ( Maximum Voltage on +12 V Pin IN Maximum Voltage Pin IN Maximum Voltage on All Open−Drain Outputs (excluding PWM pins) Maximum Voltage on TACHx/PWMx Pins Voltage on ...
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ELECTRICAL CHARACTERISTICS Parameter Power Supply Supply Voltage Supply Current Temperature−to−Digital Converter Local Sensor Accuracy Resolution Remote Diode Sensor Accuracy Remote Sensor Source Current Series Resistance Cancellation (Note 2) Analog−to−Digital Converter (Including MUX and Attentuators) Total Unadjusted Error (TUE) ...
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ELECTRICAL CHARACTERISTICS Parameter Digital I/O (PECI Pin) (Note Supply Voltage TT Input High Voltage , V IH Input Low Voltage Hysteresis (Note 2) High Level Output Source Current, I SOURCE Low Level Output Sink Current, ...
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PIN ASSIGNMENT Pin No. Mnemonic 1 SDA Digital I/O 2 SCL Digital Input 3 GND Ground 4 V Power Supply CC 5 GPIO1 Digital Input/Output 6 GPIO2 Digital Input/Output 7 PECI Digital Input/Output 8 V Analog Input TT 9 TACH3 ...
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Table 1. Comparison of ADT7490 and ADT7476A Configurations Pin No. 1 SDA 2 SCL 3 GND GPIO1 6 GPIO2 7 PECI TACH3 10 PWM2/SMBALERT 11 TACH1 12 TACH2 13 PWM3/ADDREN 14 TACH4/THERM/SMBALERT/ADDR ...
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TEMPERATURE (5C) Figure 5. Local Temperature Sensor Error 3.0 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –40 – ...
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POWER SUPPLY NOISE FREQUENCY (MHz) Figure 11. Remote Temperature Error vs. Power Supply Noise Frequency 160 140 120 100 60mV 20 0 ...
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... PECI interface. The V voltage must be connected to the ADT7490 in order for activation TT CC the PECI interface to be operational. I Monitoring MON The I MON output of ON Semiconductor’s VR10/VR11.1 controllers. http://onsemi.com 10 activation temperature and CC are user defined. CONTROL T RANGE ...
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voltage representation of the CPU current. Using MON the I value and the measured V MON CCP CPU power consumption can be calculated. See the appropriate Analog Devices flex mode data sheet for calculations. The I information ...
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SCL SDA 0 1 START BY MASTER SERIAL BUS ADDRESS BYTE Figure 18. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register 1 SCL SDA START BY MASTER SERIAL ...
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The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. For the ADT7490, the send byte protocol is used to write a register ...
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... PECI circuitry. The I input on Pin 19 can be used to monitor the I MON of ON Semiconductor’s VR11.1 controllers. I voltage representation of the CPU current. Analog−to−Digital Converter All analog inputs are multiplexed into the on−chip, successive approximation, analog−to−digital converter. ...
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Table 4. Conversion Time with Averaging Disabled Channel Measurement Time (ms) Voltage Channels Remote Temperature 1 Remote Temperature 2 Local Temperature When Bit 7 (ExtraSlow) of Configuration Register 6 (0x10) is set, the default round−robin cycle time increases to 240 ...
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Table 7. 10−Bit ADC Output Code vs <0.0156 <0.0065 <0.0042 0.0156 to 0.0065 to 0.0042 to 0.0312 0.0130 0.0085 0.0312 to 0.0130 to 0.0085 to 0.0469 0.0195 0.0128 0.0469 ...
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Temperature Measurement The ADT7490 has four temperature measurement channels: one local, two remote thermal diodes, and a PECI. The local and thermal diode readings are analog temperature measurements, whereas PECI is a digital temperature reading. PECI Temperature Measurement The PECI ...
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Table 8. PECI Error Indicators PECI Description Data 0x8000 to PECI data error 0x8003 Invalid PECI communications error FCS Each PECI channel also has an associated status bit to indicate if the PECI high or low limits have been exceeded. ...
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Table 11. Twos Complement Temperature Data Format Temperature Digital Output (10−Bit) (Note 1) –128°C 1000 0000 00 (diode fault) –63°C 1100 0001 00 –50°C 1100 1110 00 –25°C 1110 0111 00 –10°C 1111 0110 00 0°C 0000 0000 00 10.25°C ...
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I and giving DV between I and giving DV . The temperature can BE2 then be calculated using the two DV BE method can also cancel the effect of any series resistance ...
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To factor this in, the user can write the DT value to the offset register. The ADT7490 automatically adds subtracts it from the temperature measurement. • Some CPU manufacturers specify the high and low current levels of ...
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Table 13. Conversion Time with Averaging Disabled Channel Measurement Time (ms) Voltage Channels Remote Temperature 1 Remote Temperature 2 Local Temperature When Bit 7 of Configuration Register 6 (0x10) is set, the default round−robin cycle time increases to a maximum ...
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Register 0x6B, Local THERM Temperature Limit = 0x64 default Register 0x52, Remote 2 Temperature Low Limit = 0x81 default Register 0x53, Remote 2 Temperature High Limit = 0x7F default Register 0x6C, Remote 2 THERM Temperature Limit = 0x64 default Register ...
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Table 16. Interrupt Status and Interrupt Mask Register Address and Bit Assignments Interrupt Interrupt Bit 7 Status Mask Register Register 0x41 0x74 OOL 0x42 0x75 D2 FAULT 0x43 0x82 OOL 0x81 0x83 V TT SMBALERT Interrupt Behavior The ADT7490 can ...
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If THERM is enabled (Bit 1, Configuration Register 3 at Address 0x78), • Pin 22 becomes THERM. • If Pin 14 is configured as THERM (Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D), THERM is enabled ...
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If the THERM timer is read during a THERM assertion, the following happens: • The contents of the timer are cleared. • Bit 0 of the THERM timer is set to 1, because a THERM assertion is occurring. • The ...
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THERM TIMER LIMIT 364.16ms (REGISTER 0x7A) 182.08ms 91.04ms 45.52ms 22.76ms Figure 34. Functional Block Diagram of THERM Monitoring Circuitry Alternatively, OS− or BIOS−level time−stamp when the system is powered on SMBALERT is generated due to ...
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THERM Hysteresis Setting Bit 0 of Configuration Register 7 (0x11) disables THERM hysteresis. If THERM hysteresis is enabled and THERM is disabled (Bit 2 of Configuration Register 4, 0x7D), the THERM event is not reflected in the status register and ...
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TACH TACH 4.7k W ADT7490 3. PWM Figure 38. Driving a 4−Wire Fan Driving Two Fans from PWM3 The ADT7490 has four TACH inputs available for fan speed measurement, but only three PWM drive ...
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If the fan output has a resistive pullup other voltage greater than 3.6 V, the fan output can be clamped with a Zener diode, as shown in Figure 43. The Zener diode voltage should be chosen ...
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Because the actual fan TACH period is being measured, falling below a fan TACH limit by 1 sets the appropriate status bit and can be used to generate an SMBALERT. Fan TACH Limit Registers The fan TACH limit registers are ...
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PWM Logic State The PWM outputs can be programmed high for 100% duty cycle (non−inverted) or low for 100% duty cycle (inverted). PWM1 Configuration (Register 0x5C) Bit 4 (INV Logic high for 100% PWM duty cycle (non−inverted) 1 ...
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Programming the Automatic Fan Speed Control Loop To more efficiently understand the automatic fan speed control loop, using the ADT7490 evaluation board and software while reading this section is recommended. This section provides the system designer with an understanding of ...
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THERMAL CALIBRATION T MIN REMOTE 1 = THERMAL CALIBRATION AMBIENT TEMP T MIN LOCAL = THERMAL CALIBRATION VRM TEMP T MIN REMOTE 2 = THERMAL CALIBRATION GPU TEMP T MIN PECI = CPU TEMP Figure 48. Automatic Fan Control Block ...
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Automatic Fan Control Multiplexer Options Bits [7:5] (BHVR), Register 0x5C, Register 0x5D, and Register 0x5E, with the ALT bit (Bit 3) cleared to 0. 000 = Remote 1 temperature controls PWMx 001 = Local temperature controls PWMx 010 = Remote ...
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T MIN THERMAL CALIBRATION T MIN THERMAL CALIBRATION REMOTE 2 = CPU TEMP T MIN LOCAL = THERMAL CALIBRATION VRM TEMP T MIN REMOTE 1 = AMBIENT TEMP Step 4: PWM for Each PWM (Fan) Output MIN PWM ...
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PWM2 PWM1 PWM2 MIN PWM1 MIN 0% TEMPERATURE T MIN Figure 51. Operating Two Different Fans from a Single Temperature Channel Programming the PWM Registers MIN The PWM registers are 8−bit registers that allow the MIN minimum PWM duty ...
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T RANGE 100% PWM MIN 0% T TEMPERATURE MIN Figure 53. T Parameter Affects Cooling Slope RANGE The T is determined by the following procedure: RANGE 1. Determine the maximum operating temperature for that channel (for example, 70°C). 2. Determine ...
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Actual Changes in PWM Output (Advanced Acoustics Settings) While the automatic fan control algorithm describes the general response of the PWM output also necessary to note that the enhanced acoustics registers (0x62, 0x63, and 0x3C) can be used ...
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T limit runs all fans at 100%, it has THERM very negative acoustic effects. Ultimately, this limit should be set fail−safe, and one should ensure that it is not exceeded under normal system operating conditions. ...
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Step 8: T for Temperature Channels HYST T is the amount of extra cooling a fan provides after HYST the temperature measured has dropped back below T before the fan turns off. The premise for temperature hysteresis ( ...
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Bit 5 (MIN1 PWM1 is off (0% PWM duty cycle) when the temperature is below T − T MIN HYST Bit 5 (MIN1 PWM1 runs at PWM1 minimum duty cycle below T − MIN ...
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Register Tables Table 20. ADT7490 Registers Addr R/W Desc Bit 7 0x10 R/W Config. Extra Reg. 6 Slow 0x11 R/W Config. RES Reg. 7 0x12 R Extended RES Revision 0x1A R PECI1 7 0x1B R PECI2 7 0x1C R PECI3 ...
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Table 20. ADT7490 Registers Addr R/W Desc Bit 7 0x34 R/W PECI Low 7 Limit 0x35 R/W PECI 7 High Limit 0x36 R/W PECI RES Config. Register 1 0x38 R/W Max 7 PWM1 Duty Cycle 0x39 R/W Max 7 PWM2 ...
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Table 20. ADT7490 Registers Addr R/W Desc Bit 7 0x4F R/W Remote 1 7 Temp High Limit 0x50 R/W Local 7 Temp Low Limit 0x51 R/W Local 7 Temp High Limit 0x52 R/W Remote 2 7 Temp Low Limit 0x53 ...
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Table 20. ADT7490 Registers Addr R/W Desc Bit 7 0x64 R/W PWM1 7 Min Duty Cycle 0x65 R/W PWM2 7 Min Duty Cycle 0x66 R/W PWM3 7 Min Duty Cycle 0x67 R/W Remote 1 7 Temp. T MIN 0x68 R/W ...
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Table 20. ADT7490 Registers Addr R/W Desc Bit 7 0x79 R THERM TMR Timer Status 0x7A R/W THERM LIMT Timer Limit 0x7B R/W TACH FAN4 Pulses per Revolution 0x7C R/W Config. R2 Register 5 THERM THERM Output Only 0x7D R/W ...
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Table 20. ADT7490 Registers Addr R/W Desc Bit 7 0x94 R/W PECI0 7 Temp. Offset 0x95 R/W PECI1 7 Temp. Offset 0x96 R/W PECI2 7 Temp. Offset 0x97 R/W PECI3 7 Temp. Offset − 0x41 − − Table 21. Register ...
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Table 23. PECI Reading Registers (Power−On Default = 0x80) Register Address R/W 0x33 Read−only 0x1A Read−only 0x1B Read−only 0x1C Read−only Table 24 Reading Registers (Power−On Default = 0x00) MON TT Register Address R/W 0x1D Read−only 0x1E Read−only Table ...
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Table 28. Fan Tachometer Reading Registers (Power−On Default = 0x00) Register Address R/W 0x28 Read−only 0x29 Read−only 0x2A Read−only 0x2B Read−only 0x2C Read−only 0x2D Read−only 0x2E Read−only 0x2F Read−only 1. These registers count the number of 11.11 ms periods (based ...
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Table 32. Register 0x36 — PECI Configuration Register 1 (Power−On Default = 0x00) Bit No. Mnemonic R/W (Note 1) [2:0] AVG[2:0] R/W [3] DOM0 R/W [4] REPLACE R/W [7:5] RES R 1. These registers become read-only when the Configuration Register ...
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Table 35. Register 0x3C — PECI T RANGE Bit No. Mnemonic R/W (Note 1) [2:0] ACOU R/W [2:0] ACOU R/W [3] ENP R/W [7:4] RANGE R/W 1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is ...
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Table 36. T Limit Register (Power−On Default = 0x00) CONTROL Register Address R/W (Note 2) 0x3D R any PECI reading exceeds the T CONTROL incorporated to cool the system in the event of a critical overtemperature. It also ...
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Table 39. Register 0x41 — Interrupt Status Register 1 (Power−On Default = 0x00) Bit No. Mnemonic R/W [0] +2 Read−only IN THERM [1] V Read−only CCP [2] V Read−only CC [ Read−only IN [4] R1T Read−only ...
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Table 41. Register 0x43 — Interrupt Status Register 3 (Power−On Default = 0x00) Bit No. Mnemonic R/W [0] PECI0 Read−only [1] DATA Read−only [2] COMM Read−only [3] OVT Read−only (THERM Temp Limit) [6:4] RES Read−only [7] OOL Read−only Table 42. ...
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Table 44. Fan Tachometer Limit Registers Register Address R/W 0x34 R/W 0x54 R/W 0x55 R/W 0x56 R/W 0x57 R/W 0x58 R/W 0x59 R/W 0x5A R/W 0x5B R/W 1. Exceeding any of the TACH limit registers by 1 indicates that the ...
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Table 47. Register 0x5C, Register 0x5D, and Register 0x5E — PWM1, PWM2, and PWM3 Configuration Registers (Power−On Default = 0x62) Bit No. Mnemonic R/W (Note 1) [2:0] SPIN R/W [3] ALT R/W [4] INV R/W [7:5] BHVR R/W (Note 2) ...
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Table 49. Register 0x5F, Register 0x60, and Register 0x61 — Remote 1 T Local T /PWM2 Frequency, and Remote 2 T RANGE Bit No. Mnemonic R/W (Note 1) [2:0] FREQ R/W [3] HF/LF R/W [7:4] RANGE R/W 1. This register ...
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Table 50. Register 0x62 — Enhanced Acoustics Register 1 (Power−On Default = 0x00) Bit No. Mnemonic R/W (Note 1) [2:0] ACOU R/W (Note 2) [3] EN1 R/W [4] SYNC R/W [5] MIN1 R/W [6] MIN2 R/W [7] MIN3 R/W 1. ...
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Table 51. Register 0x63 — Enhanced Acoustics Register 2 (Power−On Default = 0x00) Bit No. Mnemonic R/W (Note 1) [2:0] ACOU2 R/W [3] EN2 R/W [6:4] ACOU3 R/W [7] EN3 R/W 1. This register becomes read-only when the Configuration Register ...
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Table 54. T Registers (Note 1) MIN Register Address R/W (Note 2) 0x67 R/W 0x68 R/W 0x69 R/W 1. These are the T registers for each temperature channel. When the temperature measured exceeds T MIN minimum speed and increases with ...
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Table 58. Register 0x6E — Remote 2 and PECI Temperature/T Bit No. Mnemonic R/W (Note 1) (Note 2) [3:0] HYSP R/W [7:4] HYSR2 R/W 1. Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. ...
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Table 63. Register 0x73 — Configuration Register 2 (Power−On Default = 0x00) Bit No. Mnemonic R/W (Note 1) 0 FanPresDT R/W 1 Fan1Detect Read−only 2 Fan2Detect Read−only 3 Fan3Detect Read−only 4 AVG R/W 5 ATTN R/W 6 CONV R/W 7 ...
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Table 65. Register 0x75 — Interrupt Mask Register 2 (Power−On Default = 0x00) Bit No. Mnemonic R/W [0] +12 V R/W IN [1] OOL R/W [2] FAN1 R/W [3] FAN2 R/W [4] FAN3 R/W [5] Fan4/ R/W THERM [6] D1 ...
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Table 68. Register 0x78 — Configuration Register 3 (Power−On Default = 0x00) Bit No. Mnemonic R/W (Note 1) [0] ALERT R/W Enable [1] THERM/ R/W +2.5V IN [2] BOOST R/W [3] FAST R/W [4] DC1 R/W [5] DC2 R/W [6] ...
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Table 71. Register 0x7B — TACH Pulses per Revolution Register (Power−On Default = 0x55) Bit No. Mnemonic R/W [1:0] FAN1 R/W [3:2] FAN2 R/W [5:4] FAN3 R/W [7:6] FAN4 R/W Description Sets number of pulses to be counted when measuring ...
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Table 72. Register 0x7C — Configuration Register 5 (Power−On Default = 0x01) Bit No. Mnemonic R/W (Note 1) [0] TWOS R/W COMPL [1] Temp Offset R/W [3:2] RES R/W [4] PECI R1 R/W THERM Output Only [5] R1 THERM R/W ...
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Table 73. Register 0x7D — Configuration Register 4 (Power−On Default = 0x00) Bit No. Mnemonic R/W (Note 1) [1:0] Pin 14 Func R/W [2] THERM R/W Disable [3] Max/Full on R/W THERM [4] BpAtt R/W +2 [5] BpAtt ...
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Table 77. Register 0x81 — Interrupt Status Register 4 (Power−On Default = 0x00) Bit No. Mnemonic R/W [2:0] RES Read−only [3] PECI1 Read−only [4] PECI2 Read−only [5] PECI3 Read−only [6] I Read−only MON [7] V Read−only TT Table 78. Register ...
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Table 81. Register 0x88 — PECI Configuration Register 2 (Power−On Default = 0x00) Bit No. Mnemonic R/W (Note 1) [2:0] RES R/W [3] DOM3 R/W [4] DOM2 R/W [5] DOM1 R/W [7:6] #CPU R/W 1. This register becomes read-only when ...
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Table 83. Register 0x8E — Dynamic T Bit No. Mnemonic R/W (Note 1) [0] CYR2 R/W [ R/W CCP [2] PHTR1 R/W [3] PHTL R/W [4] PHTR2 R/W [5] R1T R/W [6] LT R/W [7] R2T R/W 1. ...
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Table 84. Register 0x8F — Dynamic T Bit No. Mnemonic R/W (Note 1) [2:0] CYR1 R/W [5:3] CYL R/W [7:6] CYR2 R/W 1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any ...
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Table 85. Register 0x90 — Dynamic T Bit No. Mnemonic R/W (Note 1) [2:0] RES Reserved [5:3] CYP R/W [6] PHTP R/W [7] PECI R/W 1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set ...
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... ORDERING INFORMATION Device Order Number* ADT7490ARQZ ADT7490ARQZ-REEL ADT7490ARQZ-R7 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *These are Pb−Free packages. Package Type Package Option 24-Lead QSOP RQ−24 http://onsemi ...
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... C 0.10 C 24X *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. dBCOOL is a registered trademarks of Semiconductor Components Industries, LLC (SCILLC). Pentium is a registered trademark of Intel Corporation. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein ...