ADM1026JSTZ-REEL ON Semiconductor, ADM1026JSTZ-REEL Datasheet - Page 28
![IC CNTRL SYS REF/EEPROM 48-LQFP](/photos/7/49/74961/adm1026jstz_sml.jpg)
ADM1026JSTZ-REEL
Manufacturer Part Number
ADM1026JSTZ-REEL
Description
IC CNTRL SYS REF/EEPROM 48-LQFP
Manufacturer
ON Semiconductor
Datasheet
1.ADM1026JSTZ-R7.pdf
(55 pages)
Specifications of ADM1026JSTZ-REEL
Function
Hardware Monitor
Topology
ADC, Comparator, Multiplexer, Register Bank
Sensor Type
External & Internal
Sensing Temperature
0°C ~ 100°C, External Sensor
Output Type
SMBus™
Output Alarm
No
Output Fan
Yes
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
0°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
48-LFQFP
Full Temp Accuracy
+/- 3 C
Digital Output - Bus Interface
Serial (2-Wire)
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
ADM1026JSTZ-REEL
Manufacturer:
AD
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Company:
Part Number:
ADM1026JSTZ-REEL
Manufacturer:
ON Semiconductor
Quantity:
10 000
Part Number:
ADM1026JSTZ-REEL
Manufacturer:
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Quantity:
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Part Number:
ADM1026JSTZ-REEL7
Manufacturer:
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Quantity:
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FROM FAN SPEED
LIMIT REGISTERS
is provided. THERM is only deasserted when the measured
temperature of all three sensors is 5°C below the limit.
as shown in Figure 53. However, this is edge−triggered, so
HIGH LIMIT
HIGH LIMIT
LOW LIMIT
Whenever the THERM output changes, INT is asserted,
VALUE
VALUE AND
VALUE
FROM ANALOG/TEMP
VALUE AND LIMIT
REGISTERS
OF LIMIT
OF LIMIT
1 = OUT
1 = OUT
GPIO8 TO GPIO15
GPIO0 TO GPIO7
MASKING DATA
MASKING DATA
FROM SMBus
FROM SMBus
NAMES AND ORDER
NAMES AND ORDER
NAMES AND ORDER
NAMES AND ORDER
MASK DATA FROM
MASK DATA FROM
MASK DATA FROM
MASK DATA FROM
SMBus (SAME BIT
SMBus (SAME BIT
SMBus (SAME BIT
SMBus (SAME BIT
AS STATUS BITS)
AS STATUS BITS)
AS STATUS BITS)
AS STATUS BITS)
EXT 2 TEMP
RESERVED
EXT1 TEMP
Figure 52. Interrupt Structure
3.3V STBY
3.3V MAIN
INT TEMP
GPIO16
THERM
STATUS REGISTER 5
STATUS REGISTER 6
V
FAN0
FAN1
FAN2
FAN3
FAN4
FAN5
FAN6
FAN7
V
+12V
–12V
MASK REGISTER 5
MASK REGISTER 6
AFC
A
BAT
+5V
A
A
A
A
A
A
A
A
CCP
IN8
CI
http://onsemi.com
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
REGISTER
REGISTER
REGISTER
REGISTER
MASK
MASK
MASK
MASK
1
2
4
3
28
if INT is subsequently cleared by one of the methods
previously described, it is not reasserted, even if THERM
remains asserted. THERM causes INT to be reasserted only
when it changes state.
STATUS
BIT
MASK
BIT
STATUS
BIT
MASK
BIT
STATUS
BIT
MASK
BIT
STATUS
BIT
MASK
BIT
STATUS
BIT
MASK
BIT
STATUS
BIT
MASK
BIT
MASK GATING
MASK GATING
MASK GATING
MASK GATING
MASK GATING
MASK GATING
CI
GPIO16
INT CLEAR
IN OUT
IN OUT
LATCH
RESET
LATCH
RESET
INT ENABLE
INT