TCN75-3.3MUAG Microchip Technology, TCN75-3.3MUAG Datasheet - Page 6

• Manufacturer Part Number: TCN75-3.3MUAG
• Description: IC TEMP SENSOR SRL 3.3V 8MSOP
• Manufacturer: Microchip Technology

Specifications of TCN75-3.3MUAG

• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Register Bank
• Sensor Type: Internal
• Sensing Temperature: -55°C ~ 125°C
• Output Type: 2-Wire Serial
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Temperature Threshold: Programmable
• Full Temp Accuracy: 3 C
• Digital Output - Bus Interface: 2-Wire
• Digital Output - Number Of Bits: 9 bit
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Description/function: 2-Wire Serial Input/Output - Thermal Monitors
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Supply Current: 1 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TCN75
3.0
A typical TCN75 hardware connection is shown in
Figure 3-1.
FIGURE 3-1:
3.1
Bi-directional. Serial data is transferred in both
directions using this pin.
3.2
Input. Clocks data into and out of the TCN75.
3.3
Open Collector, Programmable Polarity. In Comparator
mode,
temperature exceeds the value programmed into the
T
temperature subsequently falls below the T
ting. (See Section 5.0, Register Set and Programmer's
Model). In Interrupt mode, INT/CMPTR is also made
active by TEMP exceeding T
RESET to its inactive state by reading any register via
the 2-wire bus. If and when temperature falls below
T
register will clear the T
the INT/CMPTR output is unconditionally RESET upon
entering Shutdown mode. If programmed as an active-
low output, it can be wire-ORed with any number of
other open collector devices. Most systems will require
a pull-up resistor for this configuration.
Note that current sourced from the pull-up resistor
causes power dissipation and may cause internal heat-
ing of the TCN75. To avoid affecting the accuracy of
ambient temperature readings, the pull-up resistor
should be made as large as possible. INT/CMPTR's
output polarity may be programmed by writing to the
INT/CMPTR POLARITY bit in the CONFIG register.
The default is active low.
DS21490B-page 6
SET
HYST
register. INT/CMPTR will become inactive when
, INT/CMPTR is again driven active. Reading any
unconditionally
DETAILED DESCRIPTION
Serial Data (SDA)
Serial Clock (SCL)
INT/CMPTR
HYST
TYPICAL APPLICATION
I 2 C ™ Interface
(Set as Desired)
driven
interrupt. In Interrupt mode,
Address
SET
; it is unconditionally
active
SDA
SCL
A 0
A 1
A 2
any
HYST
2
7
6
5
1
time
set-
TCN75
+V
8
4
DD
(3V to 5.5V)
C Bypass
3
INT/CMPTR
3.4
Inputs. Sets the three Least Significant bits of the
TCN75 8-bit address. A match between the TCN75's
address and the address specified in the serial bit
stream must be made to initiate communication with
the TCN75. Many protocol-compatible devices with
other addresses may share the same 2-wire bus.
3.5
The four Most Significant bits of the Address Byte (A6,
A5, A4, A3) are fixed to 1001[B]. The states of A2, A1
and A0 in the serial bit stream must match the states of
the A2, A1 and A0 address inputs for the TCN75 to
respond with an Acknowledge (indicating the TCN75 is
on the bus and ready to accept data). The Slave
Address is represented in Table 3-1.
TABLE 3-1:
3.6
INT/CMPTR behaves differently depending on whether
the TCN75 is in Comparator mode or Interrupt mode.
Comparator mode is designed for simple thermostatic
operation. INT/CMPTR will go active anytime TEMP
exceeds T
CMPTR will remain active until TEMP falls below
T
The state of INT/CMPTR is maintained in Shutdown
mode when the TCN75 is in Comparator mode. In
Interrupt mode, INT/CMPTR will remain active
indefinitely, even if TEMP falls below T
register is read via the 2-wire bus. Interrupt mode is
better suited to interrupt driven microprocessor-based
HYST
MSB
1
0.1µF Recommended
Unless Device is Mounted
Close to CPU
, whereupon it will RESET to its inactive state.
To Controller
Address (A2, A1, A0)
Slave Address
Comparator/Interrupt Modes
SET
0
. When in Comparator mode, INT/
TCN75 SLAVE ADDRESS
0
©
2002 Microchip Technology Inc.
1
A2
HYST
A1
, until any
LSBS
A0