ADT7483AARQZ-REEL ON Semiconductor, ADT7483AARQZ-REEL Datasheet - Page 17

• Manufacturer Part Number: ADT7483AARQZ-REEL
• Description: IC TEMP SENSOR/ALARM 3CH 16-QSOP
• Manufacturer: ON Semiconductor

Specifications of ADT7483AARQZ-REEL

• Function: Temp Monitoring System (Sensor)
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SERIAL BUS INTERFACE
Control of the ADT7483A is carried out via the serial bus. The
ADT7483A is connected to the serial bus as a slave device,
under the control of a master device.
The ADT7483A has an SMBus timeout feature. When this is
enabled, the SMBus typically times out after 25 ms of no activity.
However, this feature is not enabled by default. Bit 7 (SCL
timeout bit) of the consecutive ALERT register (Address = 0x22)
should be set to enable the SCL timeout. Bit 6 (SDA timeout bit)
of the consecutive ALERT register (Address = 0x22) should be set
to enable the SDA timeout.
The ADT7483A supports packet error checking (PEC) and its
use is optional. It is triggered by supplying the extra clock for
the PEC byte. The PEC byte is calculated using CRC-8. The
frame check sequence (FCS) conforms to CRC-8 by the
polynomial
Consult the SMBus 1.1 specification for more information
(www.smbus.org).
ADDRESSING THE DEVICE
Address Pins
In general, every SMBus device has a 7-bit device address
(except for some devices that have extended, 10-bit addresses).
When the master device sends a device address over the bus,
the slave device with that address will respond. The ADT7483A
has two address pins, ADD0 and ADD1, to allow selection of
the device address, so that several ADT7483As can be used on
the same bus, and/or to avoid conflict with other devices.
Although only two address pins are provided, these are three-
state, and can be grounded, left unconnected, or tied to V
that a total of nine different addresses are possible, as shown in
Table 16. It should be noted that the state of the address pins is
only sampled at power-up, so changing them after power-up
has no effect.
Table 16. Device Addresses
ADD1
0
0
0
NC
NC
NC
1
1
1
C
( )
x
=
x
8
+
x
2
+
x
1
0
NC
1
ADD0
0
NC
1
0
NC
1
+
1
Device Address
0011 000
0011 001
0011 010
0101 001
0101 010
0101 011
1001 100
1001 101
1001 110
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, so
The serial bus protocol operates as follows:
1.
2.
3.
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation. For the ADT7483A, write operations
contain either one or two bytes, while read operations contain
one byte.
To write data to one of the device data registers, or to read data
from it, the address pointer register must be set so that the
correct data register is addressed. The first byte of a write
operation always contains a valid address that is stored in the
address pointer register. If data is to be written to the device, the
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line (SDATA), while the serial clock line (SCLK)
remains high. This indicates that an address/data stream
follows. All slave peripherals connected to the serial bus
respond to the start condition and shift in the next eight
bits, consisting of a 7-bit address (MSB first) plus an R/W
bit, which determines the direction of the data transfer,
that is, whether data will be written to, or read from, the
slave device. The peripheral whose address corresponds to
the transmitted address responds by pulling the data line
low during the low period before the ninth clock pulse,
known as the acknowledge bit. All other devices on the bus
now remain idle while the selected device waits for data
to be read from or written to it. If the R/W bit is a 0, the
master writes to the slave device. If the R/W bit is a 1, the
master reads from the slave device.
Data is sent over the serial bus in a sequence of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, since a low-to-high transition
when the clock is high may be interpreted as a stop signal.
The number of data bytes that can be transmitted over the
serial bus in a single read or write operation is limited only
by what the master and slave devices can handle.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master will
pull the data line high during the tenth clock pulse to assert
a stop condition. In read mode, the master device will
override the acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse. This is
known as no acknowledge. The master will then take the
data line low during the low period before the tenth clock
pulse, then high during the tenth clock pulse to assert a
stop condition.
ADT7483A