LM5021MM-1/NOPB National Semiconductor, LM5021MM-1/NOPB Datasheet - Page 9

• Manufacturer Part Number: LM5021MM-1/NOPB
• Description: IC PWM CTRLR AC-DC CURR 8-MSOP
• Manufacturer: National Semiconductor

Specifications of LM5021MM-1/NOPB

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 1MHz
• Duty Cycle: 85%
• Voltage - Supply: 8 V ~ 30 V
• Buck: Yes
• Boost: Yes
• Flyback: Yes
• Inverting: Yes
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Frequency-max: 1MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM5021MM-1; LM5021MM-1TR

LM5021-1:
LM5021-2:
The LM5021 can also be synchronized to an external clock.
The external clock must have a higher frequency than the free
running oscillator frequency set by the RT resistor. The clock
signal should be capacitively coupled into the RT pin with a
100pF capacitor. A peak voltage level greater than 3.8 Volts
at the RT pin is required for detection of the sync pulse. The
dc voltage across the RT resistor is internally regulated at 2
volts. Therefore, the ac pulse superimposed on the RT resis-
tor must have 1.8V or greater amplitude to successfully syn-
chronize the oscillator. The sync pulse width should be set
between 15ns to 150ns by the external components. The RT
resistor is always required, whether the oscillator is free run-
ning or externally synchronized. The RT resistor should be
located very close to the device and connected directly to the
pins of the LM5021 (RT and GND).
GATE DRIVER and MAX DUTY CYCLE LIMIT
The LM5021 provides a gate driver (OUT), which can source
peak current of 0.3A and sink 0.7A. The LM5021 is available
in two duty-cycle limit options. The maximum output duty-cy-
cle is typically 80% for the LM5021-1 option, and precisely
equal to 50% for the LM5021-2 option. The maximum duty
cycle function for the LM5021-2 is accomplished with an in-
ternal toggle flip-flop to ensure an accurate duty cycle limit.
The internal oscillator frequency of the LM5021-2 is therefore
twice the switching frequency of the PWM controller (OUT
pin).
The 80% maximum duty-cycle function for the LM5021-1 is
determined by the internal oscillator. For the LM5021-1 the
internal oscillator frequency and the switching frequency of
the PWM controller are the same.
SOFT-START
The soft-start feature allows the power converter to gradually
reach the initial steady state operating point, thus reducing
start-up stresses and current surges. An internal 22 µA cur-
rent source charges an external capacitor connected to the
SS pin. The capacitor voltage will ramp up slowly, limiting the
COMP pin voltage and the duty cycle of the output pulses.
The soft-start capacitor is also used to generate the hiccup
mode delay time when the output of the switching power sup-
ply is continuously overloaded.
HICCUP MODE OVERLOAD CURRENT LIMITING
Hiccup mode is a method of protecting the power supply from
over-heating and damage during an extended overload con-
dition. When the output fault is removed the power supply will
automatically restart.
Figure
of the hiccup mode for LM5021 and the relevant waveforms.
3,
Figure 4
and
Figure 5
illustrate the equivalent circuit
9
During start-up and in normal operation, the external soft-start
capacitor Css is pulled up by a current source that delivers 22
µA to the SS pin capacitor. In normal operation, the soft-start
capacitor continues to charge and eventually reaches the sat-
uration voltage of the current source (V
5.2V). During start-up the COMP pin voltage follows the SS
capacitor voltage and gradually increases the peak current
delivered by the power supply. When the output of the switch-
ing power supply reaches the desired voltage, the voltage
feedback amplifier takes control of the COMP signal (via the
opto-coupler). In normal operation the COMP level is held at
an intermediate voltage between 1.25V and 2.75V controlled
by the voltage regulation loop. When the COMP pin voltage
is below 1.25V, the duty-cycle is zero. When the COMP level
is above 2.75V, the duty cycle will be limited by the 0.5V
threshold of cycle-by-cycle current limit comparator.
If the output of the power supply is overloaded, the voltage
regulation loop demands more current by increasing the
COMP pin control voltage. When the COMP pin exceeds the
over voltage detection threshold (V
SS capacitor Css will be discharged by a 10 µA overload de-
tection timer current source, I
V
Hiccup mode threshold (V
enters the hiccup mode. The OUT pin is then latched low and
the SS capacitor discharge current source is reduced from 10
µA to 0.25 µA, the dead-time current source, I
pin voltage is slowly reduced until it reaches the Restart
threshold (V
quence commences with 22 µA current source charging the
capacitor C
the Hiccup threshold to the Restart threshold provides an ex-
tended off time that reduces the overheating of components
including diodes and MOSFETs due to the continuous over-
load. The off time during the hiccup mode can be calculated
from the following equation:
Example:
Toff = 808 ms, assuming the C
Short duration intermittent overloads will not trigger the hiccup
mode. The overload duration required to trigger the hiccup
response is set by the capacitor C
current source and voltage difference between the saturation
level of the SS pin and the Hiccup mode threshold.
shows the waveform of SS pin with a short duration overload
condition. The overload time required to enter the hiccup
mode can be calculated from the following equation:
Example:
Toverload = 2.82 ms, assuming the C
0.047 µF
OVLD
long enough for the SS capacitor to discharge to the
SS
RST
. The slow discharge of the SS capacitor from
, nominally 0.3V). Then a new start-up se-
HIC
, nominally 4.6V), the controller
OVCS
SS
capacitor value is 0.047 µF
. If COMP remains above
OVLD
SS
, the 10 µA discharge
, nominally 4.6V), the
SS
capacitor value is
SS_OCV
DTCS
www.national.com
, nominally
. The SS
Figure 5