ISL8118IRZ Intersil, ISL8118IRZ Datasheet - Page 12

• Manufacturer Part Number: ISL8118IRZ
• Description: IC CTRLR PWM 1-PHASE 28-QFN
• Manufacturer: Intersil

Specifications of ISL8118IRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 100%
• Voltage - Supply: 2.97 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 2MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Undervoltage and Overvoltage Protection
The Undervoltage (UV) and Overvoltage (OV) protection
circuitry compares the voltage on the VDIFF pin with the
reference that tracks with the margining circuitry to prevent
accidental tripping. UV and OV functionality is not enabled
until the end of soft-start.
An OV event is detected asynchronously and causes the top
side MOSFET to turn off, the bottom side MOSFET to turn
on (effectively a 0% duty cycle), and PGOOD to pull low. The
regulator stays in this state and overrides sourcing and
sinking OCP protections until the OV event is cleared.
A UV event is detected asynchronously and results in the
PGOOD pulling low.
Overcurrent Protection
The ISL8118 monitors both the top side MOSFET and bottom
side MOSFET for overcurrent events. Dual sensing allows the
ISL8118 to detect overcurrent faults at the very low and very
high duty cycles that can result from the ISL8118’s wide input
range. The OCP function is enabled with the drivers at start-up
and detects the peak current during each sensing period. A
resistor and a capacitor between the BSOC pin and GND set
the bottom side source and sinking current limits. A 100µA
current source develops a voltage across the resistor which is
then compared with the voltage developed across the bottom
side MOSFET at conduction mode. The measurement
comparator uses offset correcting circuitry to provide precise
current measurements with roughly ±2mV of offset error. An
~120ns blanking period, implemented on the upper and lower
MOSFET current sensing circuitries, is used to reduce the
current sampling error due to the leading-edge switching noise.
An additional 120ns low pass filter is used to further reduce
measurement error due to noise. In sourcing current
applications, the BSOC voltage is inverted and compared with
the voltage across the MOSFET while on. When this voltage
exceeds the BSOC set voltage, a sourcing OCP fault is
triggered. A 1000pF or greater filter capacitor should be used in
T
PGDLY
FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW
=
C
UV
PGDLY
GOOD
⋅
-------------- -
30μA
1.5V
VDIFF
12
OV
GOOD
UV
V
REF_MARG
-15%
+15%
+9%
-9%
ISL8118
parallel with R
impacting the accuracy of the OCP measurement.
The ISL8118’s sinking current limit is set to the same voltage
as its sourcing limit. In sinking applications, when the voltage
across the MOSFET is greater than the voltage developed
across the resistor (RBSOC) a sinking OCP event is
triggered. To avoid non-synchronous operation at light load,
the peak-to-peak output inductor ripple current should not be
greater than twice of the sinking current limit.
The top side sourcing current limit is set by connecting the
TSOC pin with a resistor (R
of the top side MOSEFT. A 100µA current source develops a
voltage across the resistor which is then compared with the
voltage developed across the top side MOSFET while on.
When the voltage drop across the MOSFET exceeds the
voltage drop across the resistor, a sourcing OCP event
occurs. A 1000pF or greater filter capacitor should be used in
parallel with R
impacting the accuracy of the OCP measurement and to
smooth the voltage across R
switching noise on the input bus.
Sourcing OCP faults cause the regulator to disable (TGATE
and BGATE drives pulled low, PGOOD pulled low, soft-start
capacitor discharged) itself for a fixed period of time after which
a normal soft-start sequence is initiated. The period of time the
regulator waits before attempting a soft-start sequence is set by
three charge and discharge cycles of the soft-start capacitor.
Simple Top Side OCP Equation
R
Detailed Top Side OCP Equation
R
N
Simple Bottom Side OCP Equation
R
Detailed Bottom Side OCP Equations
R
ΔI =
I
N
OC_SINK
TSOC
TSOC
T
BSOC
BSOC
B
=
=
V
------------------------------- -
Number of top side MOSFETs
Number of Bottom side MOSFETs
IN
=
=
=
=
F
- V
S
=
I
------------------------------------------------------------------- -
⎛
⎝
------------------------------------------------------------------------------------ -
I
------------------------------------------------------------------------------------
⎛
⎝
-------------------------------------------------------------------------------------
OC_SOURCE
OC_SOURCE
I
I
L
OC_SOURCE
OUT
OC_SOURCE
I
--------------------------------------------------------- -
BSOC
BSOC
TSOC
•
r
V
--------------- -
DS ON
100μA
•
V
I
to prevent on chip parasitics from
OUT
I
to prevent on chip parasitics from
TSOC
BSOC
N
IN
(
100μA
B
r •
r •
•
+
+
)B
R
DS ON
DS ON
I Δ
---- -
I Δ
---- -
2
•
2
•
BSOC
TSOC
⎞
⎠
N
⎞
⎠
N
(
TSOC
(
r •
T
r •
B
DS ON
DS ON
)T
)Botside
) and a capacitor to the drain
–
(
(
I Δ
---- -
in the presence of
2
)T
)B
April 7, 2009
FN6325.1