ISL8120IRZ Intersil, ISL8120IRZ Datasheet - Page 20

• Manufacturer Part Number: ISL8120IRZ
• Description: IC CTRLR PWM 2PHASE W/DVR 32-QFN
• Manufacturer: Intersil

Specifications of ISL8120IRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1.5MHz
• Duty Cycle: 90%
• Voltage - Supply: 3 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 1.5MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VSEN1- resistor is 100Ω and it should not be large in order
to keep the unit gain amplifier input impedance compatibility.
VMON1, VMON2 (Pins 31, 11)
These pins are outputs of the unity gain amplifiers. They are
connected internally to the OV/UV/PGOOD comparators.
These pins should be connected to the FB1, FB2 pins by a
standard feedback network when both channels are operating
independently. When VSEN1-, VSEN2- are pulled within
700mV of VCC, the corresponding differential amplifier is
disabled and its output (VMON pin) is high impedance. In
such an event, the VMON pin can be used as an additional
monitor of the output voltage with a resistor divider to protect
the system against single point of failure, which occurs in the
system using the same resistor divider for both of the UV/OV
comparator and output voltage feedback.
Modes of Operation
There are 9 typical operation modes depending upon the
signal levels on EN1/FF1, EN2/FF2, VSEN2+, VSEN2-,
FB2, and CLKOUT/REFIN.
MODE 1: The IC is completely disabled when EN1/FF1 and
EN2/FF2 are pulled below 0.8V.
MODE 2: With EN1/FF1 pulled low and EN2/FF2 pulled high
(Mode 2A), or EN1/FF1 pulled high and EN2/FF2 pulled low
(Mode 2B), the ISL8120 operates as a single phase
regulator. The current sourcing out from the ISHARE pin
represents the first channel current plus 15µA offset current.
MODE 3: When VSEN2- is used as a negative sense line,
both channels’ phase shift depends upon the voltage level of
CLKOUT/REFIN. When the CLKOUT/REFIN pin is within
29% to 45% of VCC, Channel 2 delays 0° over Channel 1
(Mode 3A); when within 45% to 62% of VCC, 90°delay
(Mode 3B); when greater than 62% to VCC, 180° delay
(Mode 3C). Refer to the “DDR and Dual Mode Operation” on
page 32.
MODE 4: When VSEN2- is used as a negative remote sense
line, and CLKOUT/REFIN is connected to an external
voltage ramp lower than the internal soft-start ramp and
lower than 0.6V, the external ramp signal will replace
Channel 2’s internal soft-start ramp to be tracked at start-up,
controller operating in DDR mode. The controller will use the
lowest voltage among the internal 0.6V reference, the
external voltage in CLKOUT/REFIN pin and the soft-start
ramp signal. Channel 1 is delayed 60° behind Channel 2.
Refer to the “DDR and Dual Mode Operation” on page 32.
20
ISL8120
MODE 5: With VSEN2- pulled within 700mV of VCC and
FB2 pulled to ground, the internal channels are 180°
out-of-phase and operate in 2-phase single output mode
(5A). The CLKOUT/REFIN pin (rising edge) also signals out
clock with 60° phase shift relative to the Channel 1’s clock
signal (falling edge of PWM) for 6-phase operation with two
other ISL8120s (5B). When the share pins are not
connected to each other for the three ICs in sync, two of
which can operate in Mode 5A (3 independent outputs can
be generated (Mode 5D)) and Modes 3 and 4 (to generate 4
independent outputs (Mode 5C)) respectively.
MODE 6: With VSEN2- pulled within 700mV of VCC, FB2
pulled high and VSEN2+ pulled low, the internal channels
(as 1st and 3rd Phase, respectively) are 240° out-of-phase
and operate in 3-phase single output mode, combined with
another ISL8120 at MODE 2B. The CLKOUT/REFIN pin
signals out 120° relative phases to the falling edge of
Channel 1’s clock signal to synchronize with the second
ISL8120’s Channel 1 (as 2nd Phase).
MODE 7: With VSEN2- pulled within 700mV of VCC and
FB2 and VSEN2+ pulled high, the internal channel is 180°
out-of-phase. The CLKOUT/REFIN pin (rising edge) signals
out 90° relative phase to the Channel 1’s clock signal (falling
edge of PWM) to synchronize with another ISL8120, which
can operate at Mode 3, 4, 5A, or 7A. A 4-phase single output
converter can be constructed with two ISL8120s operating in
Mode 5A or 7A (Mode 7A). If the share bus is not connected
between ICs, each IC could generate an independent output
(Mode 7B). When the second ISL8120 operates as two
independent regulators (Mode 3) or in DDR mode (Mode 4),
then a three independent output system is generated (Mode
7C). Both ICs can also be constructed as a 3-phase
converter (0°, 90°, and 180°, not a equal phase shift for
3-phase) with a single phase regulator (270°).
MODE 8: The output CLKOUT signal allows expansion for
12-phase operation with the cascaded sequencing, as
shown in Table 1. No external clock is required in this mode
for the desired phase shift.
MODE 9: With an external clock, the part can be expanded
for 5, 7, 8, 9 10 and 11 phase single output operation with
the desired phase shift.
March 20, 2009
FN6641.0