ISL8844AABZ Intersil, ISL8844AABZ Datasheet - Page 11

• Manufacturer Part Number: ISL8844AABZ
• Description: IC PWM CTRLR SGL-ENDED 8-SOIC
• Manufacturer: Intersil

Specifications of ISL8844AABZ

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 50%
• Voltage - Supply: 9 V ~ 30 V
• Buck: Yes
• Boost: Yes
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 2MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Soft-Start Operation
Soft-start must be implemented externally. One method,
illustrated below, clamps the voltage on COMP.
The COMP pin is clamped to the voltage on capacitor C1
plus a base-emitter junction by transistor Q1. C1 is charged
from VREF through resistor R1 and the base current of Q1.
At power-up C1 is fully discharged, COMP is at ~0.7V, and
the duty cycle is zero. As C1 charges, the voltage on COMP
increases, and the duty cycle increases in proportion to the
voltage on C1. When COMP reaches the steady state
operating point, the control loop takes over and soft start is
complete. C1 continues to charge up to VREF and no longer
affects COMP. During power down, diode D1 quickly
discharges C1 so that the soft start circuit is properly
initialized prior to the next power on sequence.
Gate Drive
The ISL884xA is capable of sourcing and sinking 1A peak
current. To limit the peak current through the IC, an optional
external resistor may be placed between the totem-pole
output of the IC (OUT pin) and the gate of the MOSFET. This
small series resistor also damps any oscillations caused by
the resonant tank of the parasitic inductances in the traces of
the board and the FET’s input capacitance.
Slope Compensation
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale
current feedback signal. For applications where the duty
cycle is greater than 50%, slope compensation is required to
prevent instability.
Slope compensation may be accomplished by summing an
external ramp with the current feedback signal or by
subtracting the external ramp from the voltage feedback
error signal. Adding the external ramp to the current
feedback signal is the more popular method.
D1
C1
FIGURE 5. SOFT-START
ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A
R1
Q1
11
VREF
COMP
GND
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is in Equation 6.
Fm
where Sn is the slope of the sawtooth signal and Tsw is the
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes:
Fm
where Se is slope of the external ramp and
m
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the
damping factor of the double-pole located at the switching
frequency. The double-pole will be critically damped if the
Q-factor is set to 1, over-damped for Q < 1, and
under-damped for Q > 1. An under-damped condition may
result in current loop instability.
Q
where D is the percent of on time during a switching cycle.
Setting Q = 1 and solving for Se yields
S
Since Sn and Se are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by t
V
where Vn is the change in the current feedback signal (ΔI)
during the on time and Ve is the voltage that must be added
by the external ramp.
For a flyback converter, Vn can be solved for in terms of
input voltage, current transducer components, and primary
inductance, yielding
V
where R
frequency, L
input voltage, and D is the maximum duty cycle.
e
e
e
c
=
=
=
=
=
ON
=
=
-------------------------------------------------
π m
S
V
D T
--------------------------------------------------- -
1
(
------------------- -
SnTsw
-------------------------------------- -
(
n
n
Sn
to obtain the voltage change that occurs during t
+
⋅
⎛
⎝
⎛
⎝
CS
c
1
Se
-------
Sn
⎛
⎝
⎛
⎝
(
SW
1
-- -
π
1
-- -
π
+
1 D
+
+
Se
is the current sense resistor, f
–
1
p
1
0.5
0.5
⋅
L
is the primary inductance, V
V
)Tsw
p
) 0.5
IN
⎞
⎠
⎞
⎠
–
------------ - 1
1 D
------------ - 1
1 D
⋅
–
–
1
1
R
=
)
CS
–
–
--------------------------- -
m
⎛
⎝
c
⎛
⎝
⎞
⎠
⎞
⎠
1
-- -
π
SnTsw
1
+
0.5
⎞
⎠
------------ - 1
1 D
–
1
–
⎞
⎠
sw
IN
is the switching
is the minimum
V
April 18, 2007
(EQ. 11)
(EQ. 12)
(EQ. 10)
FN6320.3
(EQ. 9)
(EQ. 6)
(EQ. 8)
(EQ. 7)
ON
.