LM5025AMTCX/NOPB National Semiconductor, LM5025AMTCX/NOPB Datasheet - Page 9

• Manufacturer Part Number: LM5025AMTCX/NOPB
• Description: IC CTLR PWM CLAMP VOLT 16TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM5025AMTCX/NOPB

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1MHz
• Duty Cycle: 92.5%
• Voltage - Supply: 13 V ~ 90 V
• Buck: Yes
• Boost: Yes
• Flyback: Yes
• Inverting: Yes
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Frequency-max: 1MHz
• For Use With: LM5025AEVAL - BOARD EVALUATION LM5025ALM5025EVAL - EVALUATION BOARD FOR LM5025
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM5025AMTCX

Detailed Operating Description
The LM5025A is a functional variant of the LM5025 active
clamp PWM controller. The functional differences of the
LM5025A are:
The CS1 and CS2 current limit thresholds have been in-
creased to 0.5V.
The internal CS2 filter discharge device has been disabled
and no longer operates each clock cycle.
The internal V
when the line UVLO pin is below threshold.
The LM5025A PWM controller contains all of the features
necessary to implement power converters utilizing the Active
Clamp Reset technique. The device can be configured to
control either a P-Channel clamp switch or an N-Channel
clamp switch. With the active clamp technique higher effi-
ciencies and greater power densities can be realized com-
pared to conventional catch winding or RDC clamp / reset
techniques. Two control outputs are provided, the main power
switch control (OUT_A) and the active clamp switch control
(OUT_B). The active clamp output can be configured for ei-
ther a guaranteed overlap time (for P-Channel switch appli-
cations) or a guaranteed dead time (for N_Channel applica-
tions). The two internal compound gate drivers parallel both
MOS and Bipolar devices, providing superior gate drive char-
acteristics. This controller is designed for high-speed opera-
tion including an oscillator frequency range up to 1MHz and
total PWM and current sense propagation delays less than
100ns. The LM5025A includes a high-voltage start-up regu-
lator that operates over a wide input range of 13V to 90V.
Additional features include: Line Under Voltage Lockout (UV-
LO), softstart, oscillator UP/DOWN sync capability, precision
reference and thermal shutdown.
High Voltage Start-Up Regulator
The LM5025A contains an internal high voltage start-up reg-
ulator that allows the input pin (V
to the line voltage. The regulator output is internally current
limited to 20mA. When power is applied, the regulator is en-
abled and sources current into an external capacitor connect-
ed to the V
the V
V
voltage reference (REF) reaches its regulation point of 5V, the
controller outputs are enabled. The outputs will remain en-
abled until V
Out detector indicates that V
plications, an auxiliary transformer winding is connected
through a diode to the V
V
tor. Powering V
ciency while reducing the controller power dissipation.
CC
CC
pin reaches the regulation point of 7.6V and the internal
voltage above 8V to shut off the internal start-up regula-
CC
regulator is 0.1µF to 100µF. When the voltage on the
CC
CC
pin. The recommended capacitance range for
CC
falls below 6.2V or the line Under Voltage Lock
CC
and V
from an auxiliary winding improves effi-
REF
CC
pin. This winding must raise the
regulators continue to operate
IN
is out of range. In typical ap-
IN
) to be connected directly
9
When the converter auxiliary winding is inactive, external cur-
rent draw on the V
dissipated in the start-up regulator does not exceed the max-
imum power dissipation of the controller.
An external start-up regulator or other bias rail can be used
instead of the internal start-up regulator by connecting the
V
voltage into the two pins.
Line Under-Voltage Detector
The LM5025A contains a line Under Voltage Lock Out (UV-
LO) circuit. An external set-point voltage divider from Vin to
GND, sets the operational range of the converter. The divider
must be designed such that the voltage at the UVLO pin will
be greater than 2.5V when Vin is in the desired operating
range. If the undervoltage threshold is not met, both outputs
are disabled,all other functions of the controller remain active.
UVLO hysteresis is accomplished with an internal 20uA cur-
rent source that is switched on or off into the impedance of
the set-point divider. When the UVLO threshold is exceeded,
the current source is activated to instantly raise the voltage at
the UVLO pin. When the UVLO pin voltage falls below the
2.5V threshold, the current source is turned off causing the
voltage at the UVLO pin to fall. The UVLO pin can also be
used to implement a remote enable / disable function. Pulling
the UVLO pin below the 2.5V threshold disables the PWM
outputs.
PWM Outputs
The relative phase of the main (OUT_A) and active clamp
outputs (OUT_B) can be configured for the specific applica-
tion. For active clamp configurations utilizing a ground refer-
enced P-Channel clamp switch, the two outputs should be in
phase with the active clamp output overlapping the main out-
put. For active clamp configurations utilizing a high side N-
Channel switch, the active clamp output should be out of
phase with main output and there should be a dead time be-
tween the two gate drive pulses. A distinguishing feature of
the LM5025A is the ability to accurately configure either dead
time (both off) or overlap time (both on) of the gate driver out-
puts. The overlap / deadtime magnitude is controlled by the
resistor value connected to the TIME pin of the controller. The
opposite end of the resistor can be connected to either REF
for deadtime control or GND for overlap control. The internal
configuration detector senses the connection and configures
the phase relationship of the main and active clamp outputs.
The magnitude of the overlap/dead time can be calculated as
follows:
Overlap Time (ns) = 2.8 x R
Dead Time (ns) = 2.9 x R
R
CC
SET
and the V
in kΩ, Time in ns
IN
pins together and feeding the external bias
CC
line should be limited so the power
SET
SET
+20
- 1.2
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