ISL6440IAZ Intersil, ISL6440IAZ Datasheet - Page 12

• Manufacturer Part Number: ISL6440IAZ
• Description: IC CTRLR PWM DUAL 300MHZ 24QSOP
• Manufacturer: Intersil

Specifications of ISL6440IAZ

• Pwm Type: Current Mode
• Number Of Outputs: 2
• Frequency - Max: 340kHz
• Duty Cycle: 93%
• Voltage - Supply: 4.5 V ~ 24 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-QSOP
• Frequency-max: 340kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ringing. Careful component selection and proper PC board
layout minimizes the magnitude of these voltage spikes.
There are two sets of critical components in a DC/DC
converter using the ISL6440. The switching power
components and the small signal components. The
switching power components are the most critical from a
layout point of view because they switch a large amount of
energy so they tend to generate a large amount of noise.
The critical small signal components are those connected to
sensitive nodes or those supplying critical bias currents. A
multi-layer printed circuit board is recommended.
Layout Considerations
10. Route all high speed switching nodes away from the
1. The Input capacitors, Upper FET, Lower FET, Inductor
2. Use separate ground planes for power ground and small
3. The loop formed by Input capacitor, the top FET and the
4. Insure the current paths from the input capacitor to the
5. Place The PWM controller IC close to lower FET. The
6. Place VCC5 bypass capacitor very close to VCC5 pin of
7. Place the gate drive components BOOT diode and BOOT
8. The output capacitors should be placed as close to the
9. Use copper filled polygons or wide but short trace to
and Output capacitor should be placed first. Isolate these
power components on the topside of the board with their
ground terminals adjacent to one another. Place the input
high frequency decoupling ceramic capacitor very close
to the MOSFETs. Making the gate traces as short and
thick as possible will limit the parasitic inductance and
reduce the level of dv/dt seen at the gate of the lower
FETs when the upper FET turns on.
signal ground. Connect the SGND and PGND together
close of the IC. Do not connect them together anywhere
else.
bottom FET must be kept as small as possible.
MOSFET; to the output inductor and output capacitor are
as short as possible with maximum allowable trace
widths.
LGATE connection should be short and wide. The IC can
be best placed over a quiet ground area. Avoid switching
ground loop current in this area.
the IC and connect its ground to the PGND plane.
capacitors together near controller IC.
load as possible. Use short wide copper regions to
connect output capacitors to load to avoid inductance and
resistances.
connect junction of upper FET. Lower FET and output
inductor. Also keep the PHASE node connection to the IC
short. Do not unnecessary oversize the copper islands for
PHASE node. Since the phase nodes are subjected to
very high dv/dt voltages, the stray capacitor formed
between these islands and the surrounding circuitry will
tend to couple switching noise.
control circuitry.
12
ISL6440
11. Create separate small analog ground plane near the IC.
12. Ensure the feedback connection to output capacitor is
Component Selection Guidelines
MOSFET Considerations
The logic level MOSFETs are chosen for optimum efficiency
given the potentially wide input voltage range and output
power requirements. Two N-Channel MOSFETs are used in
each of the synchronous-rectified buck converters for the
PWM1 and PWM2 outputs. These MOSFETs should be
selected based upon r
and thermal management considerations.
The power dissipation includes two loss components;
conduction loss and switching loss. These losses are
distributed between the upper and lower MOSFETs
according to duty cycle (see the following equations). The
conduction losses are the main component of power
dissipation for the lower MOSFETs. Only the upper MOSFET
has significant switching losses, since the lower device turns
on and off into near zero voltage. The equations assume
linear voltage-current transitions and do not model power
loss due to the reverse-recovery of the lower MOSFET’s
body diode.
A large gate-charge increases the switching time, t
which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications.
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general, the output capacitors should be
selected to meet the dynamic regulation requirements
including ripple voltage and load transients. Selection of
output capacitors is also dependent on the output inductor,
so some inductor analysis is required to select the output
capacitors.
One of the parameters limiting the converter’s response to a
load transient is the time required for the inductor current to
slew to it’s new level. The ISL6440 will provide either 0% or
71% duty cycle in response to a load transient.
P
P
UPPER
LOWER
Connect SGND pin to this plane. All small signal
grounding paths including feedback resistors, current
limit setting resistors, SDx pull down resistors should be
connected to this SGND plane.
short and direct.
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October 4, 2005
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