ISL8120IRZ-TEC Intersil, ISL8120IRZ-TEC Datasheet - Page 18

• Manufacturer Part Number: ISL8120IRZ-TEC
• Description: IC CTRLR PWM 2/NPHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL8120IRZ-TEC

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1.5MHz
• Duty Cycle: 90%
• Voltage - Supply: 3 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ISHARE (Pin 3)
This pin is used for current sharing purposes and is
configured to current share bus representing all modules’
average current. It sources 15µA offset current plus the
average current of both channels in multiphase mode or
Channel 1’s current in independent mode. The share bus
(ISHARE pins connected together) voltage (V
an external resistor (R
current level of all active channel(s). The ISHARE bus
voltage compares with each reference voltage set by each
R
correction block of each cascaded controller. The share bus
impedance R
divided by number of active current sharing controllers).
CLKOUT/REFIN (Pin 7)
This pin has a dual function depending on the mode in which
the chip is operating. It provides clock signal to synchronize
with other ISL8120(s) with its VSEN2- pulled within 700mV
of VCC for multiphase (3-, 4-, 6-, 8-, 10-, or 12-phase)
operation. When the VSEN2- pin is not within 700mV of
VCC, ISL8120 is in dual mode (dual independent PWM
output). The clockout signal of this pin is not available in this
mode, but the ISL8120 can be synchronized to external
clock. In dual mode, this pin works as the following two
functions:
FB1, 2 (Pins 32, 10)
These pins are the inverting inputs of the error amplifiers.
These pins should be connected to VMON1, 2 with the
compensation feedback network. No direct connection
between FB and VMON pins is allowed. With VSEN2- pulled
within 700mV of VCC, the corresponding error amplifier is
disabled and the amplifier’s output is high impedance. FB2 is
one of the two pins to determine the relative phase
relationship between the internal clock of both channels and
the CLKOUT signal. See “DDR and Dual Mode Operation”
on page 30.
COMP1, 2 (Pins 1, 9)
These pins are the error amplifier outputs. They should be
connected to FB1, 2 pins through desired compensation
networks when both channels are operating independently.
When VSEN1-, 2- are pulled within 700mV of VCC, the
corresponding error amplifier is disabled and its output
(COMP pin) is high impedance. Thus, in multiphase
operations, all other SLAVE phases’ COMP pins can tie to
1. An external reference (0.6V target only) can be in place
2. The ISL8120IRZEC operates as a dual-PWM controller
ISET
of the Channel 2’s internal reference through this pin for
DDR/tracking applications (see “Internal Reference and
System Accuracy” on page 31).
for two independent regulators with selectable phase
degree shift, which is programmed by the voltage level on
REFIN (see “DDR and Dual Mode Operation” on
page 30).
and generates current share error signal for current
ISHARE
should be set as R
ISHARE
18
) represents the average
ISET
/N
ISHARE
CTRL
) set by
(R
ISL8120IRZEC
ISET
the MASTER phase’s COMP1 pin (1
modulates each phase’s PWM pulse with a single voltage
feedback loop. While the error amplifier is not disabled, an
independent compensation network is required for each
cascaded IC.
VSEN1+, 2+ (Pins 29, 13)
These pins are the positive inputs of the standard unity gain
operational amplifier for differential remote sense for the
corresponding channel (Channel 1 and 2), and should be
connected to the positive rail of the load/processor. These
pins can also provide precision output voltage trimming
capability by pulling a resistor from this pin to the positive rail
of the load (trimming down) or the return (typical
VSEN1-2-pins) of the load (trimming up). The typical input
impedance of VSEN+ with respect to VSEN- is 500kΩ. By
setting the resistor divider connected from the output voltage
to the input of the differential amplifier, the desired output
voltage can be programmed. To minimize the system
accuracy error introduced by the input impedance of the
differential amplifier, a 100Ω or less resistor is recommended
to be used for the lower leg (R
divider.
With VSEN2- pulled within 700mV of VCC, the
corresponding error amplifier is disabled and VSEN2+ is one
of the two pins to determine the relative phase relationship
between the internal clock of both channels and the
CLKOUT signal. See “DDR and Dual Mode Operation” on
page 30 for details.
VSEN1-, 2- (Pins 30, 12)
These pins are the negative inputs of standard unity gain
operational amplifier for differential remote sense for the
corresponding regulator (Channel 1 and 2), and should be
connected to the negative rail of the load/processor.
When VSEN1-, 2- are pulled within 700mV of VCC, the
corresponding error amplifier and differential amplifier are
disabled and their outputs are high impedance. Both
VSEN2+ and FB2 input signal levels determine the relative
phases between the internal controllers as well as the
CLKOUT signal. See “DDR and Dual Mode Operation” on
page 30 for details.
When configured as multiple power modules (with
independent voltage loop) operating in parallel, in order to
implement the current sharing control, a resistor needs to be
inserted between VSEN1- pin and output voltage negative
sense point (between VSEN1- and lower voltage sense
resistor), as shown in the “Typical Application VIII (Multiple
Power Modules in Parallel with Current Sharing Control)” on
page 12. This introduces a correction voltage for the
modules with lower load current to keep the current
distribution balanced among modules. The module with the
highest load current will automatically become the master
module. The recommended value for the VSEN1- resistor is
OS
) of the feedback resistor
st
phase), which
April 21, 2009
FN6763.1