MC34025DWG ON Semiconductor, MC34025DWG Datasheet - Page 9

• Manufacturer Part Number: MC34025DWG
• Description: IC CTRLR PWM DBL END HF 16SOIC
• Manufacturer: ON Semiconductor

Specifications of MC34025DWG

• Pwm Type: Voltage/Current Mode
• Number Of Outputs: 2
• Frequency - Max: 1MHz
• Duty Cycle: 45%
• Voltage - Supply: 10 V ~ 30 V
• Buck: No
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Frequency-max: 1MHz
• Duty Cycle (max): 45 %
• Output Voltage: 5.05 V to 5.15 V
• Output Current: 500 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 1000 KHz
• Operating Supply Voltage: 30 V
• Maximum Operating Temperature: + 70 C
• Fall Time: 30 ns
• Minimum Operating Temperature: 0 C
• Rise Time: 30 ns
• Synchronous Pin: Yes
• Topology: Half-Bridge, Push-Pull
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC34025DWGOS

comparator is activated. This comparator sets a latch which,
in turn, causes the Soft−Start capacitor to be discharged. In
this way a “hiccup” mode of recovery is possible in the case
of output short circuits. If a current limit resistor is used in
series with the output devices, the peak current at which the
controller will enter a “hiccup” mode is given by:
Undervoltage Lockout
The first senses V
V
the outputs can be enabled and the Soft−Start latch released.
If V
are disabled and the Soft−Start latch is activated. When the
UVLO is active, the part is in a low current standby mode
allowing the IC to have an off−line bootstrap startup circuit.
Typical startup current is 500 mA.
Output
specifically designed for direct drive of power MOSFETs.
They are capable of up to ± 2.0 A peak drive current with a
typical rise and fall time of 30 ns driving a 1.0 nF load.
With proper implementation, a significant reduction of
switching transient noise imposed on the control circuitry is
possible. The separate V
designer added flexibility in tailoring the drive voltage
independent of V
Reference
to an initial accuracy of ±1.0% at 25°C. This reference has
short circuit protection and can source in excess of 10 mA
for powering additional control system circuitry.
Design Considerations
wire−wrap or plug−in prototype boards. With high
frequency, high power, switching power supplies it is
imperative to have separate current loops for the signal paths
and for the power paths. The printed circuit layout should
contain a ground plane with low current signal and high
current switch and output grounds returning on separate
CC
If the voltage at this pin exceeds 1.4 V, the second
There are two undervoltage lockout circuits within the IC.
The MC34025 has two high current totem pole outputs
Separate pins for V
A 5.1 V bandgap reference is pinned out and is trimmed
Do not attempt to construct the converter on
CC
must exceed 9.2 V and V
falls below 8.4 V or V
CC
CC
I shutdown +
.
and the second V
C
and Power Ground are provided.
C
ref
supply input also allows the
ref
falls below 3.6 V, the outputs
R Sense
1.4 V
must exceed 4.2 V before
ref
. During power−up,
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9
paths back to the input filter capacitor. All bypass capacitors
and snubbers should be connected as close as possible to the
specific part in question. The PC board lead lengths must be
less than 0.5 inches for effective bypassing or snubbing.
Instabilities
at any given duty cycle. The instability is caused by the
current feedback loop. It has been shown that the instability
is caused by a double pole at half the switching frequency.
If an external ramp (S
of the current−sense waveform, stability can be achieved
(see Figure 21).
compensation. If too much is added, the system will start to
perform like a voltage mode regulator. All benefits of
current mode control will be lost. Figures 29A and 29B show
examples of two different ways in which external ramp
compensation can be implemented.
external ramp necessary to add that will achieve stability in
the current loop. For the following equations, the calculated
values for the application circuit in Figure 37 are also shown.
where:
In current mode control, an instability can be encountered
One must be careful not to add too much ramp
A simple equation can be used to calculate the amount of
For the application circuit: S e +
Ramp Compensation
N
P
Figure 21. Ramp Compensation
, N
S
V
R
e
A
O
S
L
S
i
S e +
= DC output voltage
= number of power transformer primary
=
= gain of the current sense network
=
= output inductor
= current sense resistance
or secondary turns
(see Figures 26, 27 and 28)
e
) is added to the on−time ramp (S
V O
L
Current Signal
Ramp Input
S
N S
N P
+
n
+
+ 0.115 V μs
(R S ) A
1.8 μ
5
i
1.25 V
16
4
( 0.3 )( 0.55 )
n
)