ISL6528CB-T Intersil, ISL6528CB-T Datasheet - Page 7

• Manufacturer Part Number: ISL6528CB-T
• Description: IC CNTRLR PWR PWM BUCK 8-SOIC
• Manufacturer: Intersil

Specifications of ISL6528CB-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 650kHz
• Duty Cycle: 100%
• Voltage - Supply: 4.5 V ~ 5.5 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 650kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ISL6528CB-TR

The linear regulator output voltage is also set by means of
an external resistor divider as shown in Figure 4. The two
resistors used to set the output voltage should not exceed a
parallel equivalent value, referred to as R
restriction is due to the manner of implementation of the soft-
start function. The following relationship must be met:
To ensure the parallel combination of the feedback resistors
meets this criteria, choose a target value for R
5kΩ and then apply the following equations:
where V
and V
output voltage of 0.8V, simply populate R5 with a value less
than 5kΩ and do not populate R6.
Converter Shutdown
Pulling and holding the FB2 pin above a typical threshold of
1.28V will shutdown both regulators. Upon release of the
FB2 pin, the regulators enter into a soft-start cycle which
brings both outputs back into regulation.
PWM Controller Feedback Compensation
A simplified representation of the voltage-mode control loop
used for output regulation by the standard buck converter is
shown in Figure 5. The output voltage, V
the negative input of the error amplifier which is regulated to
the reference voltage level, V
V
oscillator, V
signal from the PWM comparator. This signal is then used to
switch the MOSFET and produce a PWM waveform with an
amplitude of V
+3.3V
R
R6
R5
V
C
E/A
FB
OUT2
V
OUT2
FIGURE 4. OUTPUT VOLTAGE SELECTION OF THE LINEAR
OUT2
=
=
IN
, is compared with the triangle wave produced by the
=
REF
----------------------------------------
V
V
------------------ -
+
V
R5
--------------------- -
R5
OUT2
OUT2
R5
OUT2
REF
=
×
+
is the internal reference voltage, 0.8V. For an
×
OSC
R6
R6
0.8
V
–
×
REF
is the desired linear regulator output voltage
IN
V
R
<
×
, to provide a pulse-width modulated (PWM)
REF
Q2
FB
5kΩ
at the PHASE node. The square-wave


1
+
R5
------- -
R6


R5
REF
7
R6
. The error amplifier output,
DRIVE2
FB2
OUT
FB
, of 5kΩ. This
, is fed back to
FB
ISL6528
of less than
(EQ. 2)
(EQ. 3)
(EQ. 4)
ISL6528
PHASE voltage is then smoothed by the output filter, L
and C
The modulator transfer function is defined as V
The internal PWM comparator and driver circuits equate to a
DC gain block dominated by the supply voltage, V
by the peak-to-peak magnitude of the triangle wave,
The output filter components, L
overall modulator small-signal transfer function by
contributing a double pole break frequency at F
zero at F
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks Z
link between the modulator transfer function and a
controllable closed loop transfer function of V
goal of component selection for the compensation network is
to provide a loop gain with high 0dB crossing frequency
(f
difference between the closed loop phase at f
degrees.
F
F
0dB
LC
ESR
∆
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
V
=
) and adequate phase margin. Phase margin is the
OSC
=
OUT
--------------------------------------- -
2π
---------------------------------------- -
2π
ESR
OSC
×
, to produce a DC voltage level.
×
V
E/A
L
ESR
1
.
O
COMPENSATION DESIGN
1
DETAILED COMPENSATION COMPONENTS
ISL6528
×
ERROR
AMP
C
×
COMP
PWM
O
Z
C
+
FB
COMP
O
-
+
C1
V
REF
C2
DRIVER
R2
-
+
0.8V
Z
IN
IN
OUT
and Z
FB
and C
Z
V
FB
IN
FB
PHASE
C3
(PARASITIC)
. They provide the
OUT
L
Z
R1
OUT
IN
OUT
0dB
R3
, shape the
ESR
OUT
LC
C
V
/V
O
IN
and 180
OUT
and a
March 9, 2006
REF
+
/V
, divided
∆
(EQ. 5)
(EQ. 6)
E/A
V
V
FN9038.4
OUT
OUT
OSC
. The
.
.