HIP6521CB Intersil, HIP6521CB Datasheet - Page 9

• Manufacturer Part Number: HIP6521CB
• Description: IC PWM TRIPLE POWER CTRLR 16SOIC
• Manufacturer: Intersil

Specifications of HIP6521CB

• Pwm Type: Voltage Mode
• Number Of Outputs: 4
• Frequency - Max: 325kHz
• Duty Cycle: 100%
• Voltage - Supply: 4.5 V ~ 5.5 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 325kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the HIP6521) and the impedance networks Z
and Z
a closed loop transfer function with high 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180°. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 6. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
Figure 7 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high
gain peak dependent on the quality factor (Q) of the output
filter, which is not shown in Figure 6. Using the above
guidelines should yield a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the log-log graph of Figure 10 by
adding the Modulator Gain (in dB) to the Compensation Gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
The compensation gain uses external impedance networks
Z
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
F
F
F
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
FB
LC
Z1
Z2
=
and Z
=
=
FB
--------------------------------------- -
2π
-----------------------------------
2π
--------------------------------------------------------- -
2π
. The goal of the compensation network is to provide
×
×
×
IN
ST
ND
ST
ND
0dB
R
(
L
1
R
1
to provide a stable, high bandwidth (BW)
O
2 C1
S1
Zero Below Filter’s Double Pole (~75% F
Pole at the ESR Zero
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
×
×
) and adequate phase margin. Phase margin
1
C
+
O
R3
)
×
C3
F
ESR
9
F
F
=
P1
P2
---------------------------------------- -
2π
=
=
×
------------------------------------------------------ -
2π
-----------------------------------
2π
ESR
1
×
×
R
R
1
×
2
3
C
×
×
O
1
⎛
⎝
C3
C1
--------------------- -
C1
×
+
0dB
C2
C2
P2
⎞
⎠
LC
and
IN
)
HIP6521
ACPI Implementation
The three linear controllers included within the HIP6521 can
independently be shut down, in order to accommodate
Advanced Configuration and Power Interface (ACPI) power
management features.
To shut down any of the linears, one needs to pull and keep
high the respective FB pin above a typical threshold of
1.25V. One way to achieve this task is by using a logic gate
coupled through a small-signal diode. The diode should be
placed as close to the FB pin as possible to minimize stray
capacitance to this pin. Upon turn-off of the pull-up device,
the respective output undergoes a soft-start cycle, bringing
the output within regulation limits. On the regulators
implementing this feature, the parallel combination of the
feedback resistors has to be sufficiently high to allow ease of
driving from the external device. Considering the other
restriction applying to the upper range of this resistor
combination (see ‘Output Voltage Selection’ paragraph), it is
recommended the values of the feedback resistors on an
ACPI-enabled linear regulator output meet the following
constraint:
To turn off the switching regulator, use an open-drain or
open-collector device capable of pulling the OCSET pin (with
the attached R
possibility of OC trips at levels different than predicted, a
C
larger than the output capacitance of the pull-down device,
has to be used in parallel with R
Upon turn-off of the pull-down device, the switching regulator
undergoes a soft-start cycle.
2kΩ
FIGURE 7. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
OCSET
100
-20
-40
-60
80
60
40
20
0
<
R
--------------------- -
R
10
20
MODULATOR
S
S
capacitor with a value of an order of magnitude
×
+
log
GAIN
R
R
⎛
⎜
⎝
P
P
------------ -
R
100
R2
OCSET
<
F
S1
Z1
5kΩ
⎞
⎟
⎠
F
1K
LC
pull-up) below 1.25V. To minimize the
F
FREQUENCY (Hz)
Z2
F
ESR
10K
F
OCSET
P1
100K
F
P2
(1nF recommended).
1M
ERROR AMP GAIN
COMPENSATION
OPEN LOOP
CLOSED LOOP
20
October 16, 2006
10M
log
GAIN
⎛
⎜
⎝
GAIN
----------- -
V
V
FN4837.5
PP
IN
⎞
⎟
⎠