ISL6569ACR Intersil, ISL6569ACR Datasheet - Page 11

IC CTRLR PWM BUCK 2PHASE 32-QFN

ISL6569ACR

Manufacturer Part Number
ISL6569ACR
Description
IC CTRLR PWM BUCK 2PHASE 32-QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6569ACR

Pwm Type
Voltage/Current Mode
Number Of Outputs
1
Frequency - Max
2MHz
Duty Cycle
75%
Voltage - Supply
4.75 V ~ 5.25 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
0°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Frequency-max
2MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL6569ACR
Manufacturer:
INTERSIL
Quantity:
200
Part Number:
ISL6569ACR
Manufacturer:
INTERSIL
Quantity:
818
Part Number:
ISL6569ACR
Manufacturer:
INTERSIL
Quantity:
20 000
Voltage Regulation
The output of the error amplifier, V
sawtooth waveform to modulate the pulse width of the PWM
signals. The PWM signals control the timing of the Intersil
MOSFET drivers and regulate the converter output to the
specified reference voltage. Three distinct inputs to the error
amplifier determine the voltage level of V
and external circuitry which control voltage regulation is
illustrated in Figure 6.
Most multi-phase controllers simply have the output voltage
fed back to the inverting input of the error amplifier through a
resistor. The ISL6569A features an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the local controller ground
reference point, resulting in a more accurate means of
sensing output voltage. Connect the microprocessor sense
pins to the non-inverting input, VSEN, and inverting input,
RGND, of the remote-sense amplifier. The remote-sense
amplifier output, V
resistor to the inverting input of the error amplifier.
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID4
through VID0. The DAC decodes the a 5-bit logic signal
(VID) into one of the discrete voltages shown in Table 1.
Each VID input offers a 20µA pull-up to an internal 2.5V
source for use with open-drain outputs. External pull-up
resistors or active-high output stages can augment the pull-
up current sources, but a slight accuracy error can occur if
REMOTE
FIGURE 6. OUTPUT-VOLTAGE AND LOAD-LINE REGULATION
POINTS
SENSE
R
FB
R
V
EXTERNAL CIRCUIT
V
OFS
+
GND
-
OUT
DROOP
R
C
C
+
V
-
C
OFS
DIFF
COMP
VDIFF
RGND
VSEN
IOUT
OFS
, is then tied through an external
FB
11
ISL6569A INTERNAL CIRCUIT
I
REFERENCE
VOLTAGE
AVG
COMP
ERROR AMPLIFIER
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
100µA
, is compared to the
COMP
x0.1
+
-
+
+
-
. The internal
OFFSET
VOLTAGE
V
COMP
ISL6569A
they are pulled above 2.9V. The DAC-selected reference
voltage is connected to the non-inverting input of the error
amplifier.
The ISL6569A features a second non-inverting input to the
error amplifier which allows the user to directly offset the
DAC reference voltage in the positive direction only. The
offset voltage is created by an internal current source which
feeds out the OFS pin into a user selected external resistor
to ground. The resulting voltage across the resistor, V
internally divided down by ten to create the offset voltage.
This method of offsetting the DAC voltage is more accurate
than external methods of level-shifting the FB pin.The
integrating compensation network shown in Figure 6 assures
that the steady-state error in the output voltage is limited to
the error in the reference voltage (output of the DAC) plus
offset errors in the OFS current source, remote-sense and
error amplifiers. Intersil specifies the guaranteed tolerance of
the ISL6569A to include all variations in current sources,
amplifiers and the reference so that the output voltage
remains within the specified system tolerance of ±0.5% over
temperature.
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
TABLE 1. VOLTAGE IDENTIFICATION CODES
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
December 29, 2004
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
DAC
OFS
FN9092.2
, is

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