ISL6840IU-T Intersil, ISL6840IU-T Datasheet - Page 9

• Manufacturer Part Number: ISL6840IU-T
• Description: IC CTRLR PWM SGL-ENDED 8-MSOP
• Manufacturer: Intersil

Specifications of ISL6840IU-T

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 100%
• Voltage - Supply: 7.5 V ~ 14 V
• Buck: Yes
• Boost: Yes
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Frequency-max: 2MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

and the MOSFET gate charge, Qg, the average output
current can be calculated in Equation 5:
To optimize noise immunity, bypass V
ceramic capacitor as close to the VDD and GND pins as
possible.
VREF - The 5.00V reference voltage output. +1.0/-1.5%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1µF to 3.3µF capacitor to filter this output as
needed.
Functional Description
Features
The ISL684x current mode PWMs make an ideal choice for
low-cost flyback and forward topology applications. With its
greatly improved performance over industry standard parts,
it is the obvious choice for new designs or existing designs
which require updating.
Oscillator
The ISL684x family of controllers have a sawtooth oscillator
with a programmable frequency range to 2MHz, which can
be programmed with a resistor from VREF and a capacitor to
GND on the RTCT pin. (Please refer to Figure 4 for the
resistor and capacitance required for a given frequency.)
Soft-Start Operation
Soft-start must be implemented externally. One method,
illustrated in Figure 5, clamps the voltage on COMP.
Gate Drive
The ISL684x family are capable of sourcing and sinking 1A
peak current. To limit the peak current through the IC, an
optional external resistor may be placed between the
totem-pole output of the IC (OUT pin) and the gate of the
MOSFET. This small series resistor also damps any
oscillations caused by the resonant tank of the parasitic
inductances in the traces of the board and the FET’s input
capacitance.
I
OUT
=
Qg
×
f
FIGURE 5. SOFT-START
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
9
VREF
COMP
GND
DD
to GND with a
(EQ. 5)
Slope Compensation
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale
current feedback signal. For applications where the duty
cycle is greater than 50%, slope compensation is required to
prevent instability. The minimum amount of slope
compensation required corresponds to 1/2 the inductor
downslope. Adding excessive slope compensation,
however, results in a control loop that behaves more as a
voltage mode controller than as a current mode controller.
Slope compensation may be added to the CS signal shown
in Figure 7.
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V. When a
Fault is detected, OUT is disabled. When VREF exceeds
4.80V, the Fault condition clears, and OUT is enabled.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. V
bypassed directly to GND with good high frequency
capacitors.
FIGURE 6. CURRENT SENSE DOWNSLOPE
CURRENT SENSE SIGNAL
FIGURE 7. SLOPE COMPENSATION
TIME
DOWNSLOPE
RTCT
CS
VREF
DD
should be
August 7, 2008
FN9124.10