L6706TR STMicroelectronics, L6706TR Datasheet - Page 6

IC CTLR SGL PHASE VR11.1 40VFQFP

L6706TR

Manufacturer Part Number
L6706TR
Description
IC CTLR SGL PHASE VR11.1 40VFQFP
Manufacturer
STMicroelectronics
Datasheet

Specifications of L6706TR

Applications
Controller, Intel VR11.1
Voltage - Input
3.7 ~ 12 V
Number Of Outputs
1
Voltage - Output
0.03 ~ 1.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
40-VFQFN, 40-VFQFPN
Output Current
2 A
Mounting Style
SMD/SMT
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8975-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
L6706TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
L6706TR
Manufacturer:
ST
0
Part Number:
L6706TR /L6706
Manufacturer:
ST
0
Pins description and connection diagrams
2
2.1
6/47
Pins description and connection diagrams
Figure 3.
Pin description
Table 2.
1
2
3
4
5
6
7
COMP
DGND
SGND
Name
VSEN
VCC
FBG
FB
Pins connection (top view)
Pin description
VCCDR
PHASE
UGATE
LGATE
PGND
BOOT
Digital GND.
It must be connected to PGND (power ground).
All the internal references are referred to this pin.
Connect it to the PCB signal ground.
Device supply voltage pin.
The operative supply voltage is 12 V ±15%. Filter with 1 x 1 µF MLCC capacitor
vs. SGND.
Error amplifier output.
Connect with an R
pulling down this pin.
Error amplifier inverting input pin.
Connect with a resistor R
current proportional to the load current is sourced from this pin in order to
implement the droop effect.
Output voltage monitor, manages OVP/UVP protections and FB disconnection.
Connect to the positive side of the load to perform remote sense.
guidelines” Section
Connect to the negative side of the load to perform remote sense.
guidelines” Section
INT3
INT4
N.C.
N.C.
31
32
33
34
35
36
37
38
39
40
30
1
Doc ID 15698 Rev 2
29
2
28
3
F
for proper layout of this connection.
for proper layout of this connection.
27
- C
4
L6706
F
26
5
//C
FB
25
P
6
vs. VSEN and with an R
See “Droop function” Section
vs. FB pin. The device cannot be disabled by
24
7
Description
23
8
22
9
21
10
20
19
18
17
16
15
14
13
12
11
VID0
INT1
CS-
CS+
OUTEN
SSOSC/FLIMIT
OSC/FAULT
OCSET
OVPSEL
OFFSET
F
- C
F
//C
for details.
P
vs. COMP pin. A
See “Layout
See “Layout
L6706

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