DPA424GN Power Integrations, DPA424GN Datasheet - Page 15

• Manufacturer Part Number: DPA424GN
• Description: IC CONV DC-DC DPA SWITCH 8SMD
• Manufacturer: Power Integrations
• Series: DPA-Switch®r

Specifications of DPA424GN

• Applications: Converter, Power Over Ethernet and Telecom Applications
• Voltage - Input: 16 ~ 75 V
• Number Of Outputs: 1
• Voltage - Output: 220V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SMD Gull Wing
• Mounting Style: SMD/SMT
• For Use With: 596-1195 - KIT REF DES DPA 6.6W DC-DC CONV596-1009 - KIT DESIGN ACCELERATOR DC-DC596-1007 - KIT DESIGN ACCELERATOR POE CONV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output regulation is achieved by using secondary side voltage
reference, U3. The resistor divider formed by R10 and R11,
together with the reference voltage, determines the output
voltage. Diode D3 and C13 form a soft-fi nish network that,
together with the internal duty cycle and current limit soft-start
of the DPA-Switch, prevent output overshoot at start-up.
Resistor R7 ensures that the soft-fi nish capacitor is discharged
quickly when the output falls out of regulation. Control loop
response is shaped by R6, C16, R12, C14, R9, R4 and C5,
providing a wide bandwidth and good phase margin at gain
crossover. Since the PWM control in DPA-Switch is voltage mode,
no slope compensation is required for duty cycles above 50%.
Cost Effective 6.6 W Flyback Converter
The DPA-Switch fl yback power supply provides a cost effective
solution for high density PoE and VoIP DC-DC applications.
Figure 26 shows a typical implementation of a single output
fl yback converter using the DPA423G. For applications that
require input to output isolation, this simple, low component
count design delivers 6.6 W at 3.3 V from a 36 VDC to 57 VDC
input with a nominal effi ciency at 48 VDC of 80%.
Resistor R2 programs the input under-voltage and overvoltage
thresholds to 33 V and 86 V respectively. Resistors R1 and R3
program the internal device current limit. The addition of line
sense resistor R1 reduces the current limit with increasing input
voltage, preventing excessive overload output current. In this
design the overload output current varies less than ±2.5%
across the entire input voltage range. Controlling the current
limit also reduces secondary component stress and leakage
inductance spikes, allowing the use of a lower V
than 40 V) Schottky output diode, D2.
www.powerint.com
Figure 26. A Cost Effective 6.6 W, 3.3 V Flyback DC-DC Converter.
36 - 57 VDC
J1-1
J1-2
+V
100 V
-V
1 μF
C1
IN
IN
47 pF
200 V
1 MΩ
1%
C2
R1
SMAJ
150A
VR1
619 kΩ
D
S
1%
R2
CONTROL
X
L
1
3
2
F
8.66 kΩ
DPA-Switch
1%
R3
T1
C
DPA423G
RRM
U1
9, 10
6, 7
4
5
0.1 μF
(30 V rather
50 V
C3
100 Ω
R5
SL43
D2
5.1 Ω
22 μF
10 V
R4
C4
BAV19, SOD323
330 μF
6 V
C5
The primary side Zener clamp VR1 ensures the peak drain
voltage is kept below the 220 V BV
surge and overvoltage events. During normal operation, VR1
does not conduct and C2 is suffi cient to limit the peak drain
voltage.
The primary bias winding provides CONTROL pin current after
start-up. Diode D3 rectifi es the bias winding, while components
R5 and C8 reduce high frequency switching noise and prevent
peak charging of the bias voltage. Capacitor C3 provides local
decoupling of U1 and should be physically close to the
CONTROL and SOURCE pins. Energy storage for start-up and
auto-restart timing is provided by C4.
The secondary is rectifi ed by D2 and the Low ESR tantalum
output capacitors, C5-C7, minimizing switching ripple and
maximizing effi ciency. A small footprint secondary output choke
L1 and ceramic output capacitor C9 are adequate to reduce
high frequency noise and ripple to below 35 mV peak-peak
under full load conditions.
The output voltage is sensed by the voltage divider formed by
resistors R8 and R9 and is fed to the low voltage 1.24 V
reference U3. Feedback compensation is provided by R6, R7
and C11 together with C4 and R4. Capacitor C10 provides a
soft-fi nish characteristic, preventing output overshoot during
start-up.
Low Cost PoE VoIP Phone Converter
The basic circuitry to support IEEE standard 802.3af Power
over Ethernet (PoE) is straightforward. Class 0 signature and
classifi cation circuits can be implemented with a single resistor
and the required under-voltage lockout function is a voltage
D3
1 μF
50 V
C8
0.33 μF
330 μF
C10
6 V
C6
PC357
U2
CAT431L,
51 Ω
SOT23
R6
U3
1 μH, 2A
L1
330 μF
DPA422-426
6 V
DSS
C7
1 kΩ
0.1 μF
R7
C11
rating of U1 under input
34 kΩ
20 kΩ
1%
1%
R8
R9
PI-3806-061704
10 V
1 μF
C9
3.3 V, 2 A
J2-1
RTN
J2-2
Rev. S 12/07
15