L6714 STMicroelectronics, L6714 Datasheet
L6714
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L6714 Summary of contents
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... Intel VR10, VR11 and AMD 6Bit CPUs TQFP64 (Exposed Pad) Description L6714 implements a four phase step-down controller with 90º phase-shift between each phase with integrated high current drivers in a compact 10mm x 10mm body package with exposed pad ...
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... Voltage identifications (VID) codes for AMD 6BIT mode . . . . . . . . . . . . . 21 6 Reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 Configuring the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 DAC selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10 Current reading and current sharing loop . . . . . . . . . . . . . . . . . . . . . . 32 10.1 Low side current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2 Inductor current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11 Remote voltage sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2/70 L6714 ...
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... L6714 12 Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12.1 Droop function (Optional 12.2 Offset (Optional Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 14 Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 15 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 15.1 Intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 15.2 AMD mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15.3 Low-Side-Less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 16 Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 47 16.1 Under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16.2 Preliminary over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16 ...
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... CurrSense - Inductor Sense 23.3 Time constant matching error tolerance (TOB TCMatching 23.4 Temperature measurement error (VTC Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 24.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 24.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 65 25 Embedding L6714 - Based VR... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 26 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4/70 L6714 ...
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... L6714 1 Block diagram Figure 1. L6714 block diagram SS_END / PGOOD OSC / FAULT SS_OSC / REF DIGITAL SOFT START VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 / D-VID VID_SEL OUTEN OUTEN HS1 HS1 HS2 LS2 HS3 LOGIC PWM LOGIC PWM ADAPTIVE ANTI ADAPTIVE ANTI ...
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... Connections Figure 2. Pin connection (Through top view) TM SGND VCCDR4 LGATE4 PGND4 PGND2 LGATE2 VCCDR2 VCCDR3 LGATE3 PGND3 PGND1 LGATE1 VCCDR1 PHASE1 N.C. 6/ L6714 OFFSET 32 CS1- 31 CS1+ 30 CS3- 29 CS3+ 28 CS2- 27 CS2+ 26 CS4- 25 CS4+ 24 COMP DROOP 21 VSEN 20 SGND 19 SSOSC / REF 18 OUTEN L6714 ...
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... L6714 2.2 Functions Table 1. Pin functions N° Pin 1 UGATE1 2 BOOT1 3 N.C. 4 PHASE3 5 UGATE3 6 BOOT3 7 N.C. 8 PHASE2 9 UGATE2 10 BOOT2 11 N.C. 12 PHASE4 13 UGATE4 14 BOOT4 Channel 1 HS driver output. A small series resistors helps in reducing device-dissipated power. Channel 1 HS driver supply. Connect through a capacitor (100nF typ.) to PHASE1 and provide necessary Bootstrap diode ...
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... Inductor DCR Sense: connect through an R-C filter to the phase-side of the channel 4 inductor. See “Layout guidelines” Section for proper layout of this connection. Function for details. Section 16.2: Preliminary over voltage on proportionally SS See “Soft start” Section vs. VSEN and with vs. FB L6714 for and ...
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... L6714 Table 1. Pin functions N° Pin 25 CS4- 26 CS2+ 27 CS2- 28 CS3+ 29 CS3- 30 CS1+ 31 CS1- 32 OFFSET Channel 4 Current Sense Negative Input. LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Drain. Inductor DCR Sense: connect through a Rg resistor to the output-side of the channel 4 inductor. See “Layout guidelines” Section for proper layout of this connection ...
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... Function Table 10. resistor and filter with 100pF (max) to set the resistor. OVP Section for details. Table 7) or VR11 See “Configuring of each channel: the SW See “Oscillator” Section for details. See “Dynamic VID Table 6 and Table 7 (See Table 10). Table 9 on page 21 L6714 ...
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... L6714 Table 1. Pin functions N° Pin SS_END/ 46 PGOOD 47 VR_HOT 48 VR_FAN SGND 51 VCCDR4 52 LGATE4 53 PGND4 54 PGND2 55 LGATE2 56 VCCDR2 57 VCCDR3 58 LGATE3 59 PGND3 SSEND - Intel Mode. Soft Start END Signal. Open Drain Output set free after SS has finished and pulled low when triggering any protection. Pull voltage lower than 5V (typ), if not used it can be left floating ...
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... It must be connected to the HS1 mosfet source and provides return path for the HS driver of channel 1. Not internally connected. Thermal pad connects the Silicon substrate and makes good thermal contact with the PCB to dissipate the power necessary to drive the external mosfets. Connect to the PGND plane with several VIAs to improve thermal conductivity. Function L6714 ...
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... L6714 3 Electrical data 3.1 Maximum rating Table 2. Absolute maximum ratings Symbol PGNDx CC CCDRx V - BOOTx Boot voltage V PHASEx V - UGATEx V PHASEx BOOTx LGATEx, PHASEx, to PGNDx VID0 to VID7, VID_SEL All other Pins to PGNDx Static condition To PGNDx, VCC=14V, BOOTx=7V, PHASEx=-7.5V V PHASEx Positive peak voltage to PGNDx; ...
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... Input high OSC = OPEN; I DROOP OSC = OPEN; I DROOP OVP Active Min. Typ. Max 0.75 8.9 9.3 7.3 7.7 4.5 4.8 3.9 4.3 3.6 3.85 3.05 3.3 135 150 165 130 170 1 500 50 0.80 0.85 0.90 100 0.80 1.40 12 140 L6714 Unit kHz ...
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... L6714 Table 4. Electrical characteristics Symbol Parameter Reference and DAC k Output voltage accuracy VID REF Reference accuracy V Boot voltage BOOT VID Pull-up current I VID VID Pull-down current VID IL VID thresholds VID IH VID_SEL threshold VID_SEL (Intel mode) Error amplifier and remote buffer gain ...
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... OVP = 1.8V UVLO < VCC < UVLO OVP VCC VCC > UVLO & VCC OUTEN = SGND Hysteresis VSEN falling; below VID AMD mode; VSEN falling; below VID I = -4mA V rising TM V rising -4mA L6714 Min. Typ. Max. Unit 1 1.8 A 0.7 1.1 1.5 1.300 ...
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... L6714 5 VID Tables 5.1 Mapping for the Intel VR11 mode Table 5. Voltage Identification (VID) Mapping for Intel VR11 Mode VID7 VID6 800mV 400mV 5.2 Voltage Identification (VID) for Intel VR11 mode Table 6. Voltage Identification (VID) for Intel VR11 mode Output HEX Code ...
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... 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 B 7 L6714 (See Note). Output Output voltage HEX Code voltage (1) (1) 0.66875 D 7 0.26875 0.66250 D 8 0.26250 0.65625 D 9 0.25625 0.65000 D A 0.25000 0.64375 D B 0.24375 0.63750 D C 0.23750 0.63125 D D 0.23125 0.62500 ...
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... L6714 Table 6. Voltage Identification (VID) for Intel VR11 mode Output HEX Code voltage ( 1.26250 3 9 1.25625 3 A 1.25000 3 B 1.24375 3 C 1.23750 3 D 1.23125 3 E 1.22500 3 F 1.21875 1. According to VR11 specs, the device automatically regulates output voltage 19mV lower to avoid any external offset to modify the built-in 0 ...
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... VID VID VID VID VID L6714 Output voltage (1) 1.10000 1.09375 OFF OFF OFF OFF 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 ...
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... L6714 Table 7. Voltage identifications (VID) for Intel VR10 mode + 6.25mV VID VID VID VID According to VR10.x specs, the device automatically regulates output voltage 19mV lower to avoid any external offset to modify the built-in 0.5% accuracy improving TOB performances. Output regulated voltage is than what extracted from the table lowered by 19mVbuilt-in offset. VID7 doesn’t care. ...
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... Note). Output VID VID VID VID VID Voltage 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 L6714 (1) ...
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... L6714 6 Reference schematic Figure 3. Reference schematic - Intel VR10.x, VR11 inductor sense V IN GND IN VID_SEL OUTEN +5V NTC L6714 REF. SCH. (INDUCTOR - Intel Mode VCCDR1 BOOT1 56 VCCDR2 57 1 VCCDR3 UGATE1 63,64 51 PHASE1 VCCDR4 61 15 LGATE1 VCC 60 PGND1 19,50 SGND 31 Rg CS1 OVP CS1+ ...
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... Reference schematic Figure 4. Reference schematic - Intel VR10.x, VR11 LS MOSFET sense V IN GND IN 170k VID_SEL OUTEN +5V NTC L6714 REF. SCH. (MOSFET - Intel Mode) 24/ VCCDR1 BOOT1 56 VCCDR2 57 1 VCCDR3 UGATE1 63,64 51 PHASE1 VCCDR4 61 15 LGATE1 VCC 60 PGND1 19,50 SGND 31 Rg CS1 OVP CS1+ ...
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... L6714 Figure 5. Reference schematic - AMD 6BIT inductor sense V IN GND IN OUTEN +5V L6714 REF. SCH. (INDUCTOR - AMD 6BIT Mode VCCDR1 BOOT1 56 VCCDR2 57 1 VCCDR3 UGATE1 63,64 51 PHASE1 VCCDR4 61 15 LGATE1 VCC 60 PGND1 19,50 SGND 31 Rg CS1 OVP CS1+ 10 270k 16 BOOT2 DAC / CS_SEL ...
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... Reference schematic Figure 6. Reference schematic - AMD 6BIT LS MOSFET sense V IN GND IN OUTEN +5V NTC L6714 REF. SCH. (MOSFET - AMD 6BIT Mode) 26/ VCCDR1 BOOT1 56 VCCDR2 57 1 VCCDR3 UGATE1 63,64 51 PHASE1 VCCDR4 61 15 LGATE1 VCC 60 PGND1 19,50 SGND 31 Rg CS1 OVP CS1 BOOT2 DAC / CS_SEL ...
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... The Over-Current protection provided, with an OC threshold for each phase, causes the device to enter in constant current mode until the latched UVP. L6714 provides system Thermal Monitoring: through an apposite pin the device senses the temperature of the hottest component in the application driving the Warning and the Alarm signal as a consequence ...
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... DAC selection L6714 embeds a selectable DAC (through DAC/CS_SEL, regulate the output voltage with a tolerance of ±0.5% (±0.6% for AMD DAC) recovering from offsets and manufacturing variations. In case of selecting Intel Mode, the device automatically introduces a -19mV (both VRD10.x and VR11) offset to the regulated voltage in order to avoid any external offset circuitry to worsen the guaranteed accuracy and consequence, the calculated system TOB ...
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... L6714 Table 11. Intel mode configuration Pin It allows selecting the Intel Mode and, furthermore, between Inductor or LS MOSFET DAC / CS_SEL current reading. Static info, no dynamic changes allowed. It allows programming the soft-start time T SSOSC / REF See “Soft start” Section It allows selecting between VR11 DAC or VR10 ...
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... Power dissipation 9 Power dissipation L6714 embeds high current MOSFET drivers for both high side and low side MOSFET then important to consider the power the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. In addition, since the device has an exposed pad to better dissipate the power, the thermal resistance between ...
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... L6714 Figure 7. L6714 dissipated power (Quiescent + switching). 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 50 7000 6000 5000 4000 3000 2000 1000 0 50 L6714; Rgate=0; Rmosfet=0 HS=1xSTD38NH02L; LS=1xSTD90NH02L HS=2xSTD38NH02L; LS=2xSTD90NH02L HS=1xSTD55NH22L; LS=1xSTD95NH02L HS=2xSTD55NH22L; LS=2xSTD95NH02L HS=3xSTD55NH22L; LS=3xSTD95NH02L 100 150 ...
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... Current reading and current sharing loop 10 Current reading and current sharing loop L6714 embeds a flexible, fully-differential current sense circuitry that is able to read across both low side or inductor parasitic resistance or across a sense resistor placed in series to that element. The fully-differential current reading rejects noise and allows placing sensing element in different locations without affecting the measurement's accuracy ...
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... LS conduction time and holds the tracked information during the rest of the period. L6714 sources a constant 25 A bias current from the CSx+ pin: the current reading circuitry uses this pin as a reference and the reaction keeps the CSx- pin to this voltage during the reading time (an internal clamp keeps CSx+ and CSx- at the same voltage sinking from the CSx- pin the necessary current during the hold time ...
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... L R ------ - = R L Where I is the current information reproduced internally. INFOx 34/70 I PHASEx Rg NO Bias I =I CSx- INFOx Rg Current Sense dsON R L ------- - CSx- PHASEx Rg I PHASEx PHASEx R C CSx+ CSx- Rg Inductor DCR Current Sense R L ------- - INFOx INFOX PHASEx Rg L6714 ...
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... L6714 11 Remote voltage sense The device embeds a Remote Sense Buffer to sense remotely the regulated voltage without any additional external components. In this way, the output voltage programmed is regulated between the remote buffer inputs compensating motherboard or connector losses. It senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN pin with unity gain eliminating the errors ...
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... Mode Buck converter. The DROOP pin can also be connected to SGND through a resistor obtaining a voltage proportional to the delivered current usable for monitoring purposes. OFFSET can be disabled by shorting the relative pin to SGND. 36/ – – OUT REF FB DROOP VID 19mV VR10 - VR11 – REF VID AMD 6BIT L6714 (See Figure 11). The currents I OFFSET ...
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... L6714 12.1 Droop function (Optional) This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current: a static error proportional to the output current causes the output voltage to vary according to the sensed current ...
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... SGND: this current is mirrored and OFFSET Figure – OUT REF FB DROOP 1.240V ------------------ - R = OFFSET REF DROOP FB R OFFSET for the output voltage current is programmed by 12. Output voltage is then I – OFFSET is fixed by the 64k 64k COMP VSEN FBR Vcore (Remote Sense) L6714 FBG ...
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... Intel Mode the range of 1MHz to assure compatibility with the specifications while, for AMD Mode, this frequency is lowered to about 250kHz. When L6714 performs a D-VID transition in AMD Mode, DVID pin is pulled high as long as the device is performing the transition (also including the additional 32clocks delay) ...
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... Dynamic VID transitions Figure 13. Dynamic VID transitions VID Clock VID [0,7] Int. Reference T DVID out x 4 Step VID Transition Vout Slope Controlled by internal DVID-Clock Oscillator 40/70 T VID Step VID Transition Vout Slope Controlled by external driving circuit (T ) VID L6714 ...
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... Enable and disable L6714 has three different supplies: VCC pin to supply the internal control logic, VCCDRx to supply the low side drivers and BOOTx to supply the high side drivers. If the voltage at pins VCC and VCCDRx are not above the turn on thresholds specified in the ...
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... Soft start 15 Soft start L6714 implements a soft-start to smoothly charge the output filter avoiding high in-rush currents to be required to the input power supply. The device increases the reference from zero up to the programmed value in different ways according to the selected Operative Mode and the output voltage increases accordingly with closed loop regulation. ...
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... L6714 15.1 Intel mode Once L6714 receives all the correct supplies and enables, and Intel Mode has been selected, it initiates the Soft-Start phase with a T ramps BOOT waits for sec 3 then ramps up to the programmed value in T Figure 14). SSOSC defines the frequency of an internal additional Soft-Start-oscillator used to step the reference from zero up to the programmed value ...
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... AMD mode Once L6714 receives all the correct supplies and enables, and AMD Mode has been selected, it initiates the Soft-Start by stepping the reference from zero up to the programmed VID code (See Figure oscillator programmed by the OSC pin, SSOSC pin is not applicable in this case. The Soft- ...
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... L6714 Figure 16. Soft-start time for AMD mode 4 3.5 3 2.5 2 1.5 Time to 1.6000V Time to 1.1000V 1 Switching Frequency per phase 0 200 400 Rosc [kOhms] to SGND 4 3.5 3 2.5 2 1.5 Time to 1.6000V Time to 1.1000V 1 Switching Frequency per phase 0 200 400 Rosc [kOhms] to SGND Soft start ...
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... Soft start 15.3 Low-Side-Less startup In order to avoid any kind of negative undershoot on the load side during start-up, L6714 performs a special sequence in enabling LS driver to switch: during the soft-start phase, the LS driver results disabled (LS=OFF) until the HS starts to switch. This avoid the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output (See Figure 17) ...
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... Under voltage If the output voltage monitored by VSEN drops more than -750mV below the programmed reference for more than one clock period, L6714 turns off all MOSFET and latches the condition: to recover it is required to cycle Vcc or the OUTEN pin. This is independent of the selected operative mode ...
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... Output voltage monitor and protections 16.3 Over voltage and programmable OVP Once VCC crosses the turn-ON threshold and the device is enabled (OUTEN = 1), L6714 provides an Over Voltage Protection: when the voltage sensed by VSEN overcomes the OVP threshold, the controller permanently switches on all the low-side MOSFET and switches off all the high-side MOSFET in order to protect the load ...
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... L6714 17 Maximum Duty-cycle limitation The device limits the maximum duty cycle and this value is not fixed but it depends on the delivered current given by the following relationship: D max From the previous relationships the maximum duty cycle results: If the desired output characteristic crosses the limited-D output resulting voltage will start to drop after the cross-point ...
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... OCPx max SENSE max Rg = ----------------------------------------------------------------------- I OCTH min must be calculated starting from the corresponding output OCPx as follow (I must also be considered when D-VID are D-VID OUT OCP PP D VID – -------------------------- - – ----------- - + ----------------- - OUT OCP PP D VID – -------------------------- - + ----------- - + ----------------- - dsON LowSideMosfetSense InductorDCRSense is the additional current D-VID L6714 ...
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... L6714 18.1 Low side MOSFET sense over current The device detects an Over Current condition for each phase when the current information I overcomes the fixed threshold of I INFOx keeps the relative LS MOSFET on, also skipping clock cycles, until the threshold is crossed back and I ...
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... L OFF V OUT T ON(max OCPx max SENSE max Rg = ----------------------------------------------------------------------- I OCTH min I I OUT OCP -------------------------- - – ----------- - + OCPx -------------------------------------------- - max OFF Constant Current (Exploded) V OUT 0. Droop Effect Limted-T Char. ON Resulting Out. Char. UVP Threshold OCP OCPx (I = 140 A) DROOP I D VID – ----------------- - N L6714 I OUT I MAX,tot ...
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... L6714 18.2 Inductor sense over current The device detects an over current when the II Since the device always senses the current across the inductor, the I happen during the HS conduction time consequence of OCP detection, the device will turn OFF the HS MOSFET and turns ON the LSMOSFET of that phase until I the threshold or until the next clock cycle ...
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... Oscillator 19 Oscillator L6714 embeds four phase oscillator with optimized phase-shift (90º phase-shift) in order to reduce the input rms current and optimize the output filter definition. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The switching frequency for each ...
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... L6714 Figure 21. R OSC 7000 6000 5000 4000 3000 2000 1000 550 500 450 400 350 300 250 200 150 100 50 0 vs. switching frequency Fsw [kHz] Selected 150 250 350 450 550 Fsw [kHz] Programmed 100 125 150 650 750 850 ...
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... MOSFET choice, allowing the use of logic-level MOSFET. Several combination of supply can be chosen to optimize performance and efficiency of the application. Power conversion input is also flexible; 5V, 12V bus or any bus that allows the conversion (See maximum duty cycle limitations) can be chosen freely. 56/70 ), maintaining fast switching transition. dsON L6714 ...
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... L6714 21 System control loop compensation The control loop is composed by the Current Sharing control loop Average Current Mode control loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its regulation: the Current Sharing control loop equalize the currents in the inductors while the Average Current Mode control loop fixes the output voltage equal to the reference programmed by VID ...
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... REMOTE BUFFER 64k 64k FBG V OUT FBR 64k VSEN - C series network is considered for the 1 then introduced together with an integrator. This the oscillator ramp OSC //R + ESR O DROOP ---- - --------------------- - + C O ESR + (s), the transfer function has one (s) LOOP [dB ESR ( correspondence with the L- F L6714 R L ------- + ...
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... L6714 Compensation network can be simply designed placing frequency as desired obtaining (always considering that T 1/10th of the switching frequency F 21.1 Compensation network guidelines The Compensation Network design assures to having system response according to the cross-over frequency selected and to the output filter considered anyway possible to ...
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... Thermal monitor 22 Thermal monitor L6714 continuously senses the system temperature through TM pin: depending on the voltage sensed by this pin, the device sets free the VR_FAN pin as a warning and, after further temperature increase, also the VR_HOT pin as an alarm condition. These signals can be used to give a boost to the system fan (VR_FAN) and improve the VR cooling initiate the CPU low power state (VR_HOT) in order to reduce the current demand from the processor so reducing also the VR temperature ...
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... Controller tolerance (TOB controller) It can be further sliced as follow: ● Reference tolerance. L6714 is trimmed during the production stage to ensure the output voltage to be within k line variations. In addition, the device automatically adds a -19mV offset (Only for Intel Mode) avoiding the use of any external component. This offset is already included ...
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... Variations in the inductor DCR impacts on the output DCR ). Variations in the Rg resistors impacts Variations in the NTC nominal value at room NTC_0 ). NTC variations from room to hot also impacts on NTC DCR ------------- - + -------- - CurrSense AVP N N current different DROOP ). Total error AVP NTC -------------------------------------- - NTC0 DCR L6714 ...
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... L6714 23.3 Time constant matching error tolerance (TOB TCMatching) ● Inductance and capacitance Tolerance (k in the value of the capacitor used for the Time Constant Matching causes over/under shoots after a load transient appliance. This impacts the output voltage and then the TOB. Since all the sense elements results parallel, the error related to the time constant mismatch has to be divided by the number of phases (N). ● ...
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... Two kind of critical components and connections have to be considered when layouting a VRM based on L6714: power components and connections and small signal components connections. 24.1 ...
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... L6714 24.2 Small signal components and connections These are small signal components and connections to critical nodes of the application as well as bypass capacitors for the device supply capacitor (VCC, VCCDRx and Bootstrap capacitor) close to the device and refer sensible components such as frequency set-up resistor R resistor R to SGND ...
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... Embedding L6714 - Based VR 25 Embedding L6714 - Based VR When embedding the VRD into the application, additional care must be taken since the whole VRD is a switching DC/DC regulator and the most common system in which it has to work is a digital system such similar. In fact, latest MB has become faster and powerful: high speed data bus are more and more common and switching-induced noise produced by the VRD can affect data integrity if not following additional layout guidelines ...
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... L6714 26 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... L6714 inch Min Typ Max 0.0472 0.002 0.006 0.0374 0.0393 0.0413 0.0066 0.0086 0.0086 0.0035 0.0078 0.464 0.472 0.480 0.386 ...
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... L6714 27 Revision history Table 14. Revision history Date 16-Mar-2006 02-Aug-2006 07-Nov-2006 Revision 1 Initial release. Updated IDROOP 2 characteristics on page Updated D2 and E2 exposed tab measures in 3 TQFP64 mechanical Revision history Changes values in Table 4: Electrical IOFFSET 14. Table 13: data. 69/70 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 70/70 Please Read Carefully: © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com L6714 ...