ISL6334DCRZ Intersil, ISL6334DCRZ Datasheet - Page 17

• Manufacturer Part Number: ISL6334DCRZ
• Description: IC CTRLR PWM 4PHASE VR11.1 40QFN
• Manufacturer: Intersil

Specifications of ISL6334DCRZ

• Applications: Controller, Intel VR11.1
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Once the desired output offset voltage has been determined,
use Equations 8 and 9 to calculate R
For Positive Offset (connect R
For Negative Offset (connect R
Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R
used. The selection of R
voltage, as detailed in “Output-Voltage Offset Programming”
on page 16. The selection of C
duration for 1-bit VID change and the allowable delay time.
R
R
OFS
OFS
FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING
=
=
0.4
----------------------------- -
1.6
----------------------------- -
V
V
1.6V
OFFSET
OFFSET
×
×
R
R
VCC
+
-
REF
REF
REF
0.4V
and C
E/A
GND
+
-
REF
REF
FB
17
is based on the desired offset
, as shown in Figure 7, can be
OFS
REF
OFS
to VCC):
DYNAMIC
is based on the time
to GND):
VID D/A
OFS
ISL6334D
:
OFS
DAC
GND
VCC
OR
(EQ. 8)
(EQ. 9)
REF
R
R
C
REF
OFS
REF
ISL6334D
Assuming the microprocessor controls the VID change at
1-bit every t
of R
During dynamic VID transition and VID step-up, the
overcurrent trip point increases by 140% to avoid falsely
triggering OCP circuits, while the overvoltage trip point is set
to its maximum VID OVP trip level. If the dynamic VID occurs
at PSI# asserted, the system should exit PSI# and complete
the transition, and then resume PSI# operation 50µs after
the transition.
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts
logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6334D
is released from shutdown mode.
When all conditions previously mentioned are satisfied,
ISL6334D begins the soft-start and ramps the output voltage
to 1.1V first. After remaining at 1.1V for some time, ISL6334D
reads the VID code at VID input pins. If the VID code is valid,
ISL6334D will regulate the output to the final VID setting. If the
VID code is OFF code, ISL6334D will shut down, and cycling
VCC, EN_PWR or EN_VTT is needed to restart.
C
1. The bias voltage applied at VCC must reach the internal
2. The ISL6334D features an enable input (EN_PWR) for
3. The voltage on EN_VTT must be higher than 0.875V to
REF
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6334D are guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
ISL6334D will not inadvertently turn off unless the bias
voltage drops substantially (see “Electrical
Specifications” table beginning on page 6).
power sequencing between the controller bias voltage
and another voltage rail. The enable comparator holds
the ISL6334D in shutdown until the voltage at EN_PWR
rises above 0.875V. The enable comparator has about
130mV of hysteresis to prevent bounce. It is important
that the driver reaches its POR level before the ISL6334D
becomes enabled. The schematic in Figure 8
demonstrates sequencing the ISL6334D with the
ISL66xx family of Intersil MOSFET drivers, which require
12V bias.
enable the controller. This pin is typically connected to the
output of VTT VR.
REF
R
REF
and C
VID
=
REF
, the relationship between the time constant
t
VID
network and t
VID
is given by Equation 10.
August 31, 2010
(EQ. 10)
FN6802.2