ISL6561CRZ Intersil, ISL6561CRZ Datasheet - Page 18

• Manufacturer Part Number: ISL6561CRZ
• Description: IC CTRLR PWM MULTIPHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6561CRZ

• Applications: Controller, Intel VR10X
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 4
• Voltage - Output: 0.84 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Input Voltage: 12V
• Output Voltage: 1.65V
• Supply Voltage Range: 4.75V To 5.25V
• Digital Ic Case Style: QFN
• No. Of Pins: 40
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Control Mode: Voltage
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I1 R
- +O
V E 5
F O - V ID
V - 1
-+ D O
P 7 S
I
µs
µAIA
For example, a regulator with 250kHz switching frequency
having VID set to 1.35V has t
A 100mV offset exists on the remote-sense amplifier at the
beginning of soft start and ramps to zero during the first 640
cycles of soft start (704 cycles following enable). This
prevents the large inrush current that would otherwise occur
should the output voltage start out with a slight negative
bias.
During the first 640 cycles of soft start (704 cycles following
enable) the DAC voltage increments the reference in 25mV
steps. The remainder of soft start sees the DAC ramping
with 12.5mV steps.
Fault Monitoring and Protection
The ISL6561 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 11
outlines the interaction between the fault monitors and the
power good signal.
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that transitions high when the converter is operating after
soft start. PGOOD pulls low during shutdown and releases
high after a successful soft start. PGOOD only transitions
low when an under-voltage condition is detected or the
controller is disabled by a reset from EN, ENLL, POR, or one
of the no-CPU VID codes. After an under voltage event,
PGOOD will return high unless the controller has been
disabled. PGOOD does not automatically transition low upon
detection of an overvoltage condition.
18
SS
equal to 6.912ms.
Under-Voltage Detection
The under-voltage threshold is set at 75% of the VID code.
When the output voltage at VSEN is below the under-voltage
threshold, PGOOD gets pulled low.
Overvoltage Protection
When VCC is above 1.4V, but otherwise not valid as defined
under Power on Reset in Electrical Specifications, the
overvoltage trip circuit is active using auxiliary circuitry. In
this state, an overvoltage trip occurs if the voltage at VSEN
exceeds 1.8V.
With valid VCC, the overvoltage circuit is sensitive to the
voltage at VDIFF. In this state, the trip level is 1.7V prior to
valid enable conditions being met as described in Enable
and Disable. The only exception to this is when the IC has
been disabled by an overvoltage trip. In that case the
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May 12, 2005
FN9098.5