ISL62884CIRTZ Intersil, ISL62884CIRTZ Datasheet - Page 18

• Manufacturer Part Number: ISL62884CIRTZ
• Description: IC REG PWM SGL PHASE 28TQFN
• Manufacturer: Intersil

Specifications of ISL62884CIRTZ

• Applications: Controller, Intel IMVP-6
• Voltage - Input: 4.5 ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 ~ 1.5 V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A typical set of parameters that provide good
temperature compensation are: R
R
(ERT-J1VR103J). The NTC network parameters may need
to be fine tuned on actual boards. One can apply full load
DC current and record the output voltage reading
immediately; then record the output voltage reading
again when the board has reached the thermal steady
state. A good NTC network can limit the output voltage
drift to within 2mV. It is recommended to follow the
Intersil evaluation board layout and current-sensing
network parameters to minimize engineering time.
V
controller to achieve good transient response. Transfer
function A
to match ω
frequencies. By forcing ω
the solution, Equation 11 gives C
FIGURE 11. DESIRED LOAD TRANSIENT RESPONSE
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN C
FIGURE 13. LOAD TRANSIENT RESPONSE WHEN C
C
p
Cn
n
= 11kΩ, R
(s) also needs to represent real-time I
=
-------------------------------------------------------------- -
R
----------------------------------------- -
R
ntcnet
ntcnet
cs
L
(s) has a pole ω
WAVEFORMS
TOO SMALL
TOO LARGE
and ω
×
+
ntcs
R
R
L
sum
sum
= 2.61kΩ and R
sns
×
DCR
so A
L
18
cs
equal to ω
V
V
V
i
i
i
sns
o
o
o
o
o
o
(s) is unity gain at all
and a zero ω
n
ntc
sum
value.
sns
= 10kΩ
= 1.82kΩ,
and solving for
o
(s) for the
L
. One needs
(EQ. 11)
ISL62884C
n
n
IS
IS
For example, given R
R
L = 1.5µH, Equation 11 gives C
Assuming the compensator design is correct, Figure 11
shows the expected load transient response waveforms if
C
a square change, the output voltage V
square response.
If C
accurately represent real-time I
transient response. Figure 12 shows the load transient
response when C
upon load insertion and may create a system failure.
Figure 13 shows the transient response when C
large. V
There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU
reliability.
Figure 14 shows the output voltage ring back problem
during load transient response. The load current i
fast step change, but the inductor current i
accurately follow. Instead, i
system fashion due to the nature of current loop. The
ESR and ESL effect of the output capacitors makes the
output voltage V
However, the controller regulates V
droop current i
of i
causing the ring back problem. This phenomenon is not
observed when the output capacitors have very low ESR
and ESL, such as all ceramic capacitors.
Figure 15 shows two optional circuits for reduction of the
ring back. R
R
beginning of i
effect at steady state. Through proper selection of R
and C
V
100Ω. C
transient response waveforms on an actual board. The
recommended range for C
it should be noted that the R
the i
real inductor current, i
which may adversely affect i
detection and therefore may affect OCP accuracy. User
discretion is advised.
o
ntcs
n
i
FIGURE 14. OUTPUT VOLTAGE RING BACK PROBLEM
, providing a lower impedance path than R
L
will not ring back. The recommended value for R
is correctly selected. When the load current I
n
; therefore it pulls V
droop
value is too large or too small, V
= 2.61kΩ, R
ip
core
values, i
ip
should be determined through tuning the load
waveform. Instead of being triangular as the
ip
RING
BACK
is sluggish in drooping to its final value.
o
and C
droop
change. R
droop
o
i
n
O
ntc
dip quickly upon load current change.
is too small. V
ip
, which is a real-time representation
= 10kΩ, DCR = 19.7mΩ and
sum
can resemble i
form an R-C branch in parallel with
i
L
droop
o
ip
= 1.82kΩ, R
back to the level dictated by i
ip
L
and C
is 100pF~2000pF. However,
responds in first order
may have sharp spikes,
droop
ip
n
o
V
-C
(s) and will worsen the
core
= 0.055µF.
O
ip
ip
o
do not have any
average value
o
according to the
branch may distort
will sag excessively
p
Cn
rather than i
core
= 11kΩ,
(s) will not
also has a
L
i
cannot
at the
March 16, 2010
n
core
is too
o
FN7591.0
L
has a
, and
ip
ip
has
is
L
,