ISL6236AIRZ Intersil, ISL6236AIRZ Datasheet - Page 7

• Manufacturer Part Number: ISL6236AIRZ
• Description: IC MAIN PWR CTRLR QUAD 32-QFN
• Manufacturer: Intersil

Specifications of ISL6236AIRZ

• Applications: Controller, Notebook Computers
• Voltage - Input: 4.5 ~ 25 V
• Number Of Outputs: 4
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

Pin Descriptions
PIN
10
12
13
14
15
16
17
18
19
20
11
1
2
3
4
5
6
7
8
9
LDOREFIN LDO Reference Input. Connect LDOREFIN to GND for fixed 5V operation. Connect LDOREFIN to VCC for fixed 3.3V
UGATE1
PHASE1
EN LDO
LGATE1
BOOT1
SECFB
VREF3
NAME
PVCC
OUT1
POK1
ILIM1
TON
VCC
REF
LDO
BYP
EN1
FB1
VIN
2V Reference Output. Bypass to GND with a 0.1µF (min) capacitor. REF can source up to 50µA for external loads.
Loading REF degrades FB and output accuracy according to the REF load-regulation error.
Frequency Select Input. Connect to GND for 400kHz/500kHz operation. Connect to REF (or leave OPEN) for
400kHz/300kHz operation. Connect to VCC for 200kHz/300kHz operation (5V/3.3V SMPS switching frequencies,
respectively).
Analog Supply Voltage Input for PWM Core. Bypass to GND with a 1µF ceramic capacitor.
LDO Enable Input. The LDO is enabled if EN LDO is within logic high level and disabled if EN LDO is less than the logic
low level.
3.3V Reference Output. VREF3 can source up to 5mA for external loads. Bypass to GND with a 0.01µF capacitor if
loaded. Leave open if there is no load.
Power-Supply Input. VIN is used for the constant-on-time PWM on-time one-shot circuits. VIN is also used to power the
linear regulators. The linear regulators are powered by SMPS1 if OUT1 is set greater than 4.78V and BYP is tied to
OUT1. Connect VIN to the battery input and bypass with a 1µF capacitor.
Linear-Regulator Output. LDO can provide a total of 100mA external loads. The LDO regulates at 5V If LDOREFIN is
connected to GND. When the LDO is set at 5V and BYP is within 5V switchover threshold, the internal regulator shuts
down and the LDO output pin connects to BYP through a 0.7Ω switch. The LDO regulates at 3.3V if LDOREFIN is
connected to VCC. When the LDO is set at 3.3V and BYP is within the 3.3V switchover threshold, the internal regulator
shuts down and the LDO output pin connects to BYP through a 1.5Ω switch. Bypass LDO output with a minimum of
4.7µF ceramic.
operation. LDOREFIN can be used to program LDO output voltage from 0.7V to 4.5V. LDO output is two times the
voltage of LDOREFIN. There is no switchover in adjustable mode.
BYP is the switchover source voltage for the LDO when LDOREFIN is connected to GND or VCC. Connect BYP to 5V
if LDOREFIN is tied to GND. Connect BYP to 3.3V if LDOREFIN is tied to VCC.
SMPS1 Output Voltage-Sense Input. Connect to the SMPS1 output. OUT1 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS1 feedback input in fixed-voltage mode.
SMPS1 Feedback Input. Connect FB1 to GND for fixed 5V operation. Connect FB1 to VCC for fixed 1.5V operation.
Connect FB1 to a resistive voltage-divider from OUT1 to GND to adjust the output from 0.7V to 5.5V.
SMPS1 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM1 over a
0.2V to 2V range. There is an internal 5µA current source from VCC to ILIM1. Connect ILIM1 to REF for a fixed 200mV
threshold. The logic current limit threshold is default to 100mV value if ILIM1 is higher than VCC - 1V.
SMPS1 Power-Good Open-Drain Output. POK1 is low when the SMPS1 output voltage is more than 10% below the
normal regulation point or during soft-start. POK1 is high impedance when the output is in regulation and the soft-start
circuit has terminated. POK1 is low in shutdown.
SMPS1 Enable Input. The SMPS1 is enabled if EN1 is greater than the logic high level and disabled if EN1 is less than
the logic low level. If EN1 is connected to REF, the SMPS1 starts after the SMPS2 reaches regulation (delay start). Drive
EN1 below 0.8V to clear fault level and reset the fault latches.
High-Side MOSFET Floating Gate-Driver Output for SMPS1. UGATE1 swings between PHASE1 and BOOT1.
Inductor Connection for SMPS1. PHASE1 is the internal lower supply rail for the UGATE1 high-side gate driver.
PHASE1 is the current-sense input for the SMPS1.
Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor according to the “Typical Application
Circuits” on page 19 (Figures 66, 67 and 68). See “MOSFET Gate Drivers (UGATE, LGATE)” on page 29.
SMPS1 Synchronous-Rectifier Gate-Drive Output. LGATE1 swings between GND and PVCC.
PVCC is the supply voltage for the low-side MOSFET driver LGATE. Connect a 5V power source to the PVCC pin and
bypass to PGND with a 1µF MLCC ceramic capacitor. Refer to Figure 70 - A switch connects PVCC to VCC with 10Ω
when in normal operation and is disconnected when in shutdown mode. An external 10Ω resistor from PVCC to VCC
is prohibited as it will create a leakage path from VIN to GND in shutdown mode.
The SECFB is used to monitor the optional external 14V charge pump. Connect a resistive voltage-divider from 14V
charge pump output to GND to detect the output. If SECFB drops below the threshold voltage, LGATE1 turns on for
300ns. This will refresh the external charge pump driven by LGATE1 without over-discharging the output voltage.
7
ISL6236A
FUNCTION
March 18, 2008
FN6453.3