EL5225IRZ-T13 Intersil, EL5225IRZ-T13 Datasheet - Page 6

• Manufacturer Part Number: EL5225IRZ-T13
• Description: IC VREF GEN 10CH TFT-LCD 24TSSOP
• Manufacturer: Intersil

Specifications of EL5225IRZ-T13

• Applications: Converter, TFT, LCD
• Voltage - Input: 5 ~ 16.5 V
• Number Of Outputs: 10
• Voltage - Output: 0.5 ~ 14.95 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To facilitate the system designs that use multiple EL5225
chips, a buffered serial output of the shift register (SDO pin)
is available. Data appears on the SDO pin at the 16th falling
SCLK edge after being applied to the SDI pin.
To control the multiple EL5225 chips from a single three-wire
serial port, just connect the ENA pins and the SCLK pins
together, connect the SDO pin to the SDI pin on the next
chip. While the ENA is held low, the 16m-bit data is loaded to
the SDI input of the first chip. The first 16-bit data will go to
the last chip and the last 16-bit data will go to the first chip.
While the ENA is held high, all addressed outputs will be
updated simultaneously.
The Serial Timing Diagram and parameters table show the
timing requirements for three-wire signals.
The serial data has a minimum length of 16 bits, the MSB
(most significant bit) is the first bit in the signal. The bits are
allocated to the following functions (also refer to the Control
Bits Logic Table)
• Bit 15 is always set to a zero
• Bit 14 controls the source of the clock, see the next
• Bits 13 through 10 select the channel to be written to,
• The 10-bit data is on bits 9 through 0. Some examples of
Serial Timing Diagram
section for details
these are binary coded with channel A = 0, and channel
H = 7
data words are shown in the table of Serial Programming
Examples
SCLK
ENA
SDI
t
HE
t
SD
6
t
SE
MSB
B15
t
HD
Load MSB first, LSB last
B14
T
B13
EL5225
B12-B2
t
r
t
w
B1
B15
B14
B13
B12
B11
B10
BIT
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
t
f
TABLE 1. CONTROL BITS LOGIC TABLE
LSB
B0
t
HE
Oscillator
NAME
Test
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0
t
SE
Always 0
0 = Internal, 1 = External
Channel Address
Channel Address
Channel Address
Channel Address
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
DESCRIPTION
t
March 11, 2004
FN7356.0