ISL6333CCRZ Intersil, ISL6333CCRZ Datasheet - Page 32

• Manufacturer Part Number: ISL6333CCRZ
• Description: IC CTRLR PWM 3PHASE BUCK 48-QFN
• Manufacturer: Intersil

Specifications of ISL6333CCRZ

• Applications: Controller, Intel VR11
• Voltage - Input: 5 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 26,
the required time for this commutation is t
approximated associated power loss is P
At turn-on, the upper MOSFET begins to conduct and this
transition occurs over a time t
approximate power loss is P
A third component involves the lower MOSFET
reverse-recovery charge, Q
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P
Finally, the resistive part of the upper MOSFET is given in
Equation 29 as P
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 26, 27, 28 and 29. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controllers. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W
at room temperature. See “Layout Considerations” on
page 37 for thermal transfer improvement suggestions.
P
P
P
P
UP 2 ( )
UP 3 ( )
UP 4 ( )
UP 1 ( )
≈
≈
≈
=
V
r
V
DS ON
V
IN
IN
IN
(
⋅
⋅
⎛
⎜
⎝
⋅
⎛
⎝
I
----- -
Q
I
----- -
N
N
M
M
)
rr
⋅
UP(4).
–
+
d
⋅
I
--------- -
I
--------- -
f
P-P
⋅
P-P
2
S
2
⎛
⎜
⎝
⎞
⎟
⎠
I
----- -
N
⎞
⎠
.
M
⋅
⋅
⎞
⎟
⎠
⎛
⎜
⎝
⎛
⎜
⎝
2
t
----
2
t
----
2
2
+
1
rr
⎞
⎟
⎠
UP(2)
⎞
⎟
⎠
. Since the inductor current has
32
I
--------- -
2
⋅
P-P
12
⋅
. In Equation 27, the
f
f
S
2
UP(3)
S
.
ISL6333, ISL6333A, ISL6333B, ISL6333C
shown in Equation 28.
UP(1)
1
and the
.
rr
, it is
(EQ. 26)
(EQ. 27)
(EQ. 28)
(EQ. 29)
When designing the controllers into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, P
the gate charge of MOSFETs and the integrated driver’s
internal circuitry and their corresponding average driver current
can be estimated with Equations 30 and 31, respectively.
In Equations 30 and 31, P
power loss and P
loss; the gate charge (Q
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I
quiescent current with no load at both drive outputs; N
N
respectively; N
I
without capacitive load and is typically 75mW at 300kHz.
P
Q
P
P
I
Q2
FIGURE 21. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
DR
FIGURE 20. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
Qg_TOT
PVCC
*VCC product is the quiescent power of the controller
Qg_Q2
Qg_Q1
PVCC
are the number of upper and lower MOSFETs per phase,
=
⎛
⎝
3
-- - Q
2
PHASE
=
=
=
⋅
R
R
Q
3
-- - Q
2
LO2
P
BOOT
HI2
G1
G2
R
⋅
Qg_Q1
R
PHASE
LO1
HI1
⋅
G1
⋅
N
Qg_Q2
PVCC F
Q1
⋅
+
PVCC F
LGATE
+
P
is the number of active phases. The
Q
Qg_Q2
UGATE
G1
⋅
is the total lower gate drive power
G2
Qg_Q1
SW
⋅
and Q
⋅
N
SW
⋅
+
Q2
N
R
I
Q
Q2
⋅
is the total upper gate drive
G2
⎞ N
⎠
G2
R
N
G
⋅
⋅
G1
VCC
Q1
⋅
) is defined at the
G
N
Q
PHASE
R
C
PHASE
⋅
GI2
GD
R
is the driver total
N
C
C
GI1
GD
PHASE
GS
C
GS
⋅
F
S
Qg_TOT
SW
S
D
October 8, 2010
+
D
I
Q
Q
(EQ. 31)
C
, due to
(EQ. 30)
Q1
2
FN6520.3
DS
Q
C
1
DS
and