EL5325AIREZ Intersil, EL5325AIREZ Datasheet - Page 6

• Manufacturer Part Number: EL5325AIREZ
• Description: IC VOLT GEN 12CH TFT-LCD 28TSSOP
• Manufacturer: Intersil

Specifications of EL5325AIREZ

• Applications: Converter, TFT, LCD
• Voltage - Input: 5 ~ 16.5 V
• Number Of Outputs: 12
• Voltage - Output: 0.5 ~ 14.95 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
The EL5325A provides a versatile method of providing the
reference voltages that are used in setting the transfer
characteristics of LCD display panels. The V/T
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear; however, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the EL5325A,
the V/T curve can be changed to optimize its characteristics
according to the required application of the display product.
Each of the eight reference voltage outputs can be set with a
10-bit resolution. These outputs can be driven to within
50mV of the power rails of the EL5325A. As all of the output
buffers are identical, it is also possible to use the EL5325A
for applications other than LCDs where multiple voltage
references are required that can be set to 10 bit accuracy.
Digital Interface
The EL5325A uses a simple 3-wire SPI compliant digital
interface to program the outputs. The EL5325A can support
the clock rate up to 5MHz.
Serial Interface
The EL5325A is programmed through a three-wire serial
interface. The start and stop conditions are defined by the
ENA signal. While the ENA is low, the data on the SDI (serial
data input) pin is shifted into the 16-bit shift register on the
positive edge of the SCLK (serial clock) signal. The MSB (bit
15) is loaded first and the LSB (bit 0) is loaded last (see
Table 1). After the full 16-bit data has been loaded, the ENA
is pulled high and the addressed output channel is updated.
The SCLK is disabled internally when the ENA is high. The
SCLK must be low before the ENA is pulled low.
To facilitate the system designs that use multiple EL5325A
chips, a buffered serial output of the shift register (SDO pin)
is available. Data appears on the SDO pin at the 16th falling
SCLK edge after being applied to the SDI pin.
To control the multiple EL5325A chips from a single three-
wire serial port, just connect the ENA pins and the SCLK
pins together, connect the SDO pin to the SDI pin on the
next chip. While the ENA is held low, the 16m-bit data is
loaded to the SDI input of the first chip. The first 16-bit data
will go to the last chip and the last 16-bit data will go to the
first chip. While the ENA is held high, all addressed outputs
will be updated simultaneously.
The Serial Timing Diagram and parameters table show the
timing requirements for three-wire signals.
The serial data has a minimum length of 16 bits, the MSB
(most significant bit) is the first bit in the signal. The bits are
6
EL5325A
allocated to the following functions (also refer to the Control
Bits Logic Table)
• Bit 15 is always set to a zero
• Bit 14 controls the source of the clock, see the next
• Bits 13 through 10 select the channel to be written to,
• The 10-bit data is on bits 9 through 0. Some examples of
section for details
these are binary coded with channel A = 0, and channel
H = 7
data words are shown in the table of Serial Programming
Examples
B15
B14
B13
B12
B11
B10
BIT
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
TABLE 1. CONTROL BITS LOGIC TABLE
Oscillator
NAME
Test
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0
Always 0
0 = Internal, 1 = External
Channel Address
Channel Address
Channel Address
Channel Address
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
DESCRIPTION