EL5325AIREZ-T13 Intersil, EL5325AIREZ-T13 Datasheet - Page 8
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EL5325AIREZ-T13
Manufacturer Part Number
EL5325AIREZ-T13
Description
IC VREF GEN 12CH TFT-LCD 28-TSSO
Manufacturer
Intersil
Datasheet
1.EL5325AIRZ.pdf
(12 pages)
Specifications of EL5325AIREZ-T13
Applications
Converter, TFT, LCD
Voltage - Input
5 ~ 16.5 V
Number Of Outputs
12
Voltage - Output
0.5 ~ 14.95 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Block Diagram
Analog Section
TRANSFER FUNCTION
The transfer function is:
where data is the decimal value of the 10-bit data binary
input code.
The output voltages from the EL5325A will be derived from
the reference voltages present at the V
pins. The impedance between those two pins is about 32kΩ.
Care should be taken that the system design holds these two
reference voltages within the limits of the power rails of the
EL5325A. GND < V
In some LCD applications that require more than 12
channels, the system can be designed such that one
EL5325A will provide the Gamma correction voltages that
are more positive than the V
EL5325A can provide the Gamma correction voltage more
negative than the V
shows a system connected in this way.
V
OUT IDEAL )
(
=
V
REFL
REFH
COM
+
data
------------ -
1024
potential. The Application Drawing
≤ V
LOAD
S
COM
CLK
×
SDI
8
and GND ≤ V
(
V
REFH
potential. The second
- V
REFL
REFL
REFL
CHANNEL
MEMORY
and V
FILTER
EIGHT
)
≤ V
REFH
REFH
.
CONTROL IF
EL5325A
SOURCES
VOLTAGE
CLOCK OSCILLATOR
The EL5325A requires an internal clock or external clock to
refresh its outputs. The outputs are refreshed at the falling
OSC clock edges. The output refreshed switches open at the
rising edges of the OSC clock. The driving load shouldn’t be
changed at the rising edges of the OSC clock. Otherwise, it
will generate a voltage error at the outputs. This clock may be
input or output via the clock pin labeled OSC. The internal
clock is provided by an internal oscillator running at
approximately 21kHz and can be output to the OSC pin. In a 2
chip system, if the driving loads are stable, one chip may be
programmed to use the internal oscillator; then the OSC pin
will output the clock from the internal oscillator. The second
chip may have the OSC pin connected to this clock source.
For transient load application, the external clock Mode
should be used to ensure all functions are synchronized
together. The positive edge of the external clock to the OSC
pin should be timed to avoid the transient load effect. The
Application Drawing shows the LCD H rate signal used, here
the positive clock edge is timed to avoid the transient load of
the column driver circuits.
After power on, the chip will start with the internal oscillator
mode. At this time, the OSC pin will be in a high impedance
condition to prevent contention. By setting B14 to high, the
EXT_OSC
REFERENCE HIGH
OUTA
OUTB
OUTJ
OUTK
OUTL
REFERENCE LOW
REFERENCE DECOUPLE
SDO