MAX17004ETJ+ Maxim Integrated Products, MAX17004ETJ+ Datasheet - Page 14

• Manufacturer Part Number: MAX17004ETJ+
• Description: IC PS CTRLR FOR NOTEBOOKS 32TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17004ETJ+

• Applications: Controller, Notebook Computers
• Voltage - Input: 6 ~ 26 V
• Number Of Outputs: 4
• Voltage - Output: 3.3V, 5V, 2 ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
14
PIN
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
______________________________________________________________________________________
DSCHG3
PGDALL
NAME
PGND
LDO5
CSH3
BST5
BST3
CSL3
DH5
DH3
DL5
DL3
FB3
LX5
LX3
IN
Boost Flying Capacitor Connection for the 5V SMPS. The MAX17003/MAX17004 include an internal boost
switch connected between LDO5 and BST5. Connect to an external capacitor as shown in Figure 1.
High-Side Gate-Driver Output for the 5V SMPS. DH5 swings from LX5 to BST5.
Inductor Connection for the 5V SMPS. Connect LX5 to the switched side of the inductor. LX5 serves as the
lower supply rail for the DH5 high-side gate driver.
Low-Side Gate-Driver Output for the 5V SMPS. DL5 swings from PGND to LDO5.
Power Ground
5V Internal Linear-Regulator Output. Bypass with 4.7µF minimum (1µF/25mA). Provides at least 100mA for
the DL_ low-side gate drivers, the DH_ high-side drivers through the BST switches, the PWM controller,
logic, reference, and external loads. If CSL5 is greater than 4.5V and soft-start is complete, the linear
regulator shuts down, and LDO5 connects to CSL5 through a 1Ω switch rated for loads up to 200mA.
Input of the Startup Circuitry and the LDO5 Internal 5V Linear Regulator. Bypass to PGND with a 0.22µF or
greater ceramic capacitor close to the IC.
Open-Drain Power-Good Output for SMPS3 and SMPS5. PGDALL is pulled low if either SMPS3 or SMPS5
output drops more than 10% (typ) below the normal regulation point, or if either ON3 or ON5 are low.
PGDALL becomes high impedance when both SMPS3 and SMPS5 are in regulation.
Low-Side Gate-Driver Output for the 3.3V SMPS. DL3 swings from PGND to LDO5.
Inductor Connection for the 3.3V SMPS. Connect LX3 to the switched side of the inductor. LX3 serves as the
lower supply rail for the DH3 high-side gate driver.
High-Side Gate-Driver Output for the 3.3V SMPS. DH3 swings from LX3 to BST3.
Boost Flying Capacitor Connection for the 3.3V SMPS. The MAX17003/MAX17004 include an internal boost
switch connected between LDO5 and BST3. Connect to an external capacitor as shown in Figure 1.
Open-Drain Discharge Output for the 3.3V SMPS. DSCHG3 is pulled low when ON3 is low, discharging the
SMPS3 output. DSCHG3 is also low under fault conditions.
Connect a resistor from DSCHG3 to the SMPS3 output. Limit the peak discharge current to less than 100mA:
where R
Output Sense and Negative Current Sense for the 3.3V SMPS. When using the internal preset 3.3V feedback
divider (FB3 = LDO5), the controller uses CSL3 to sense the output voltage. Connect to the negative
terminal of the current-sense element.
Positive Current-Sense Input for the 3.3V SMPS. Connect to the positive terminal of the current-sense
element. Figure 7 describes two different current-sensing options—using accurate sense resistors or
lossless inductor DCR sensing.
Feedback Input for the 3.3V SMPS. Connect to LDO5 for fixed 3.3V output. In adjustable mode, FB3
regulates to 2V.
DSCHG3(MIN)
is 5Ω, taken from the Electrical Characteristics.
R
DIS
3
≥
100
V
OUT
mA
3
−
R
DSCHG MIN
FUNCTION
3
(
)
Pin Description (continued)