ADP3157JR-REEL Analog Devices Inc, ADP3157JR-REEL Datasheet - Page 11

• Manufacturer Part Number: ADP3157JR-REEL
• Description: IC CNTRL SYNC PENTIUM III 16SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADP3157JR-REEL

• Rohs Status: RoHS non-compliant
• Applications: Controller, Intel Pentium® III
• Voltage - Input: 12V
• Number Of Outputs: 1
• Voltage - Output: 1.3 ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)

4.
5.
6.
7.
8.
9.
Power Circuitry
10. The switching power path should be routed on the PCB to
11. A power Schottky diode (1 ~ 2 A dc rating) placed from the
REV. A
If critical signal lines (including the voltage and current
sense lines of the ADP3157) must cross through power
circuitry, it is best if a signal ground plane can be inter-
posed between those signal lines and the traces of the
power circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of making signal
ground a bit noisier.
The PGND pin of the ADP3157 should connect first to a
ceramic bypass capacitor (on the V
power ground plane using the shortest possible trace. How-
ever, the power ground plane should not extend under
other signal components, including the ADP3157 itself. If
necessary, follow the preceding guideline to use the signal
plane as a shield between the power ground plane and the
signal circuitry.
The AGND pin of the ADP3157 should connect first to the
timing capacitor (on the C
ground plane. In cases where no signal ground plane can be
used, short interconnections to other signal ground cir-
cuitry in the power converter should be used—the compen-
sation capacitor being the next most critical.
The output capacitors of the power converter should be
connected to the signal ground plan even though power
current flows in the ground of these capacitors. For this
reason, it is advised to avoid critical ground connections (e.g.,
the signal circuitry of the power converter) in the signal
ground plane between the input and output capacitors. It
is also advised to keep the planar interconnection path short
(i.e., have input and output capacitors close together).
The output capacitors should also be connected as closely
as possible to the load (or connector) that receives the
power (e.g., a microprocessor core). If the load is distrib-
uted, the capacitors also should be distributed, and gen-
erally in proportion to where the load tends to be more
dynamic.
Absolutely avoid crossing any signal lines over the switching
power path loop, described below.
encompass the smallest possible area in order to minimize
radiated switching noise energy (i.e., EMI). Failure to take
proper precaution often results in EMI problems for the
entire PC system as well as noise related operational prob-
lems in the power converter control circuitry. The switching
power path is the loop formed by the current path through
the input capacitors, the two FETs, and the power Schottky
diode if used, including all interconnecting PCB traces and
planes. The use of short and wide interconnection traces is
especially critical in this path for two reasons: it minimizes
the inductance in the switching loop, which can cause high-
energy ringing, and it accommodates the high current de-
mand with minimal voltage loss.
lower FET’s source (anode) to drain (cathode) will help to
minimize switching power dissipation in the upper FET. In
the absence of an effective Schottky diode, this dissipation
occurs through the following sequence of switching events.
The lower FET turns off in advance of the upper FET
turning on (necessary to prevent cross-conduction). The
T
pin), and then into the signal
CC
pin) and then into the
–11–
12. A small ferrite bead inductor placed in series with the drain
13. Whenever a power dissipating component (e.g., a power
14. The output power path, though not as critical as the switch-
15. For best EMI containment, the power ground plane should
Signal Circuitry
16. The output voltage is sensed and regulated between the
17. The SENSE+ and SENSE– traces should be Kelvin con-
circulating current in the power converter, no longer find-
ing a path for current through the channel of the lower
FET, draws current through the inherent body-drain diode
of the FET. The upper FET turns on, and the reverse
recovery characteristic of the lower FET’s body-drain diode
prevents the drain voltage from being pulled high quickly.
The upper FET then conducts very large current while it
momentarily has a high voltage forced across it, which
translates into added power dissipation in the upper FET.
The Schottky diode minimizes this problem by carrying a
majority of the circulating current when the lower FET is
turned off, and by virtue of its essentially nonexistent re-
verse recovery time.
of the lower FET can also help to reduce this previously
described source of switching power loss.
MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately sur-
rounding it, is recommended. Two important reasons for
this are: improved current rating through the vias (if it is a
current path), and improved thermal performance—espe-
cially if the vias extended to the opposite side of the PCB
where a plane can more readily transfer the heat to the air.
ing power path, should also be routed to encompass a small
area. The output power path is formed by the current path
through the inductor, the current sensing resistor, the out-
put capacitors, and back to the input capacitors.
extend fully under all the power components except the
output capacitors. These are: the input capacitors, the
power MOSFETs and Schottky diode, the inductor, the
current sense resistor and any snubbing elements that
might be added to dampen ringing. Avoid extending the
power ground under any other circuitry or signal lines,
including the voltage and current sense lines.
AGND pin (which connects to the signal ground plane)
and the SENSE– pin. The output current is sensed (as a
voltage) and regulated between the SENSE– pin and the
SENSE+ pin. In order to avoid differential mode noise
pickup in those sensed signals, their loop areas should be
small. Thus the SENSE– trace should be routed atop the
signal ground plane, and the SENSE+ and SENSE– traces
should be routed as a closely coupled pair (SENSE+ should
be over the signal ground plane as well).
nected to the current sense resistor so that the additional
voltage drop due to current flow on the PCB at the current
sense resistor connections does not affect the sensed volt-
age. It is desirable to have the ADP3157 close to the output
capacitor bank and not in the output power path, so that
any voltage drop between the output capacitors and the
AGND pin is minimized, and voltage regulation is not
compromised.
ADP3157