EL7585AILZ-T7 Intersil, EL7585AILZ-T7 Datasheet - Page 11

• Manufacturer Part Number: EL7585AILZ-T7
• Description: IC POWER SUPPLY TFT-LCD 20-QFN
• Manufacturer: Intersil

Specifications of EL7585AILZ-T7

• Applications: Converter, TFT, LCD
• Voltage - Input: 3 ~ 5 V
• Number Of Outputs: 4
• Voltage - Output: 5.5 ~ 20 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Operation of the DELB Output Function
An open drain DELB output is provided to allow the boost
output voltage, developed at C
to be delayed via an external switch (Q4) to a time after the
V
have achieved regulation during the start-up sequence
shown in Figure 28. This then allows the A
supplies to start-up from 0V instead of the normal offset
voltage of V
When DELB is activated by the start-up sequencer, it sinks
50µA allowing a controlled turn-on of Q4 and charge-up of
C
reduce inrush current into C
by R
required by the voltage rating of this device. When the
voltage at DELB falls to less than 0.6V, the sink current is
increased to ~1.2mA to firmly pull DELB to 0V.
The voltage at DELB is monitored by the fault protection
circuit so that if the initial 50µA sink current fails to pull DELB
below ~0.6V after the start-up sequencing has completed,
then a fault condition will be detected and a fault time-out
ramp will be initiated on the C
Operation of the PG Output Function
The PG output consists of an internal pull-up PMOS device
to V
current limited pull-down NMOS device which sinks ~15µA
allowing a controlled turn-on of Q1 gate capacitance. C
used to control how fast Q1 turns-on - limiting inrush current
into C
0.6V, the PG sink current is increased to ~1.2mA to firmly
pull the pin to 0V.
The voltage at PG is monitored by the fault protection circuit
so that if the initial 15µA sink current fails to pull PG below
~0.6V after the start-up sequencing has completed, then a
fault condition will be detected and a fault time-out ramp will
be initiated on the C
Cascaded MOSFET Application
A 20V N-channel MOSFET is integrated in the boost
regulator. For the applications where the output voltage is
greater than 20V, an external cascaded MOSFET is needed
as shown in Figure 20. The voltage rating of the external
MOSFET should be greater than V
BOOST
9
. C
IN
9
16
1
, to turn-off the external Q1 protection switch and a
and R
. When the voltage at the PG pin falls to less than
can be used to control the turn-on time of Q4 to
supply and negative V
IN
8
-V
can be used to limit the V
DIODE
DEL
(D
capacitor (C
1
) if Q4 were not present.
9
11
. The potential divider formed
DEL
2
OFF
(see application diagram),
capacitor (C
BOOST
charge pump supply
7
).
GS
.
VDD
voltage of Q4 if
7
and V
).
ON
O
is
EL7585A
Linear-Regulator Controllers (V
V
The EL7585A includes three independent linear-regulator
controllers, in which two are positive output voltage (V
and V
V
applications circuits are shown in Figures 21, 22, and 23
respectively.
Calculation of the Linear Regulator Base-Emitter
Resistors (R
For the pass transistor of the linear regulator, low frequency
gain (Hfe) and unity gain freq. (f
datasheet. The pass transistor adds a pole to the loop
transfer function at f
phase margin at low frequency, the best choice for a pass
device is often a high frequency low gain switching
transistor. Further improvement can be obtained by adding a
base-emitter resistor R
Block Diagram), which increase the pole frequency to:
f
lowest value R
enough base current (I
current (I
We will take as an example the V
Fairchild FMMT549 PNP transistor is used as the external
pass transistor, Q5 in the application diagram, then for a
maximum V
sheet indicates Hfe_min = 100.
The base-emitter saturation voltage is: Vbe_max = 1.25V
(note this is normally a Vbe ~ 0.7V, however, for the Q5
transistor an internal Darlington arrangement is used to
increase it's current gain, giving a 'base-emitter' voltage of
2 x V
(Note that using a high current Darlington PNP transistor for
Q5 requires that V
voltage be required, then an ordinary high gain PNP
transistor should be selected for Q5 so as to allow a lower
collector-emitter saturation voltage).
p
LOGIC
FIGURE 20. CASCADED MOSFET TOPOLOGY FOR HIGH
OFF
V
=f
IN
T
*(1+ Hfe *re/R
BE
LOGIC
)
).
linear-regulator controller functional diagrams,
C
).
LOGIC
), and one is negative. The V
OUTPUT VOLTAGE APPLICATIONS
BL
BE
EL7585A
, R
in the design as long as there is still
IN
operating requirement of 500mA the data
BE
p
BP
=f
> V
)/Hfe, where re=KT/qIc. So choose the
B
T
BE
/Hfe. Therefore, in order to maintain
) to support the maximum output
LOGIC
and R
(R
LX
BP
, R
T
+ 2V. Should a lower input
BN
) are usually specified in the
LOGIC
BL
)
, R
FB
ON
BN
linear regulator. If a
, V
ON
in the Functional
LOGIC
, V
OFF
March 9, 2006
, and
, and
V
BOOST
FN7523.3
ON