L6730TR STMicroelectronics, L6730TR Datasheet - Page 35

• Manufacturer Part Number: L6730TR
• Description: IC CTRLR ADJ STEP DOWN 20-TSSOP
• Manufacturer: STMicroelectronics
• Type: Step-Down (Buck)r

Specifications of L6730TR

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: Adj to 0.6V
• Frequency - Switching: 100kHz ~ 1MHz
• Voltage - Input: 1.8 ~ 14 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP Exposed Pad, 20-eTSSOP, 20-HTSSOP
• Output Voltage: 0.6 V
• Input Voltage: 1.8 V to 14 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• For Use With: 497-5868 - EVAL BOARD 30A 400KHZ L6730497-5501 - EVAL BOARD FOR L6730XX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-5098-2

L6730 - L6730B
6.4
Compensation network
The loop is based on a voltage mode control
the internal/external reference voltage and scaled by the external resistor divider. The error
amplifier output V
pulse-width modulated (PWM) with an amplitude of V
is filtered by the output filter. The modulator transfer function is the small signal transfer
function of V
L-Cout resonance and a zero at F
Gain of the modulator is simply the input voltage V
voltage: V
Figure 29. Compensation network
The compensation network consists in the internal error amplifier, the impedance networks
Z
provide a closed loop transfer function with the highest 0dB crossing frequency to have
fastest transient response (but always lower than fsw/10) and the highest gain in DC
conditions to minimize the load regulation error. A stable control loop has a gain crossing the
IN
(R3, R4 and C20) and Z
OSC
OUT
.
/V
COMP
COMP
. This function has a double pole at frequency F
is then compared with the oscillator triangular wave to provide a
FB
Doc ID 11938 Rev 3
(R5, C18 and C19). The compensation network has to
Z
ESR
FB
depending on the output capacitor’s ESR. The DC
(Figure
IN
29). The output voltage is regulated to
divided by the peak-to-peak oscillator
IN
at the PHASE node. This waveform
Z
IN
LC
Application details
depending on the
35/52