LT1977EFE#TR Linear Technology, LT1977EFE#TR Datasheet - Page 20

• Manufacturer Part Number: LT1977EFE#TR
• Description: IC REG SW 1.5A HV STPDWN 16TSSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LT1977EFE#TR

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.2 ~ 54 V
• Current - Output: 1.5A
• Frequency - Switching: 500kHz
• Voltage - Input: 3.3 ~ 60 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

a limited amount of drive capability and is susceptible to
noise during start-up and Burst Mode operation. If erratic
operation occurs during these conditions a small filter
capacitor from the PGOOD pin to ground will ensure
proper operation. Figure 10 shows several different con-
figurations for the LT1977 Power Good circuitry.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path, shown
in Figure 11, must be kept as short as possible. This is
LT1977
APPLICATIO S I FOR ATIO
20
GND
V
C1
OUT
GND
C3
+
MINIMIZE
V
IN
D1-C3
LOOP
Figure 11. High Speed Switching Path
C2
V
IN
D1
4
C2
L1
Figure 12. Suggested Layout
C4
V
D2
IN
U
CIRCULATION
LT1977
FREQUENCY
1
2
3
4
5
6
7
8
PLACE VIA's UNDER EXPOSED
PAD TO A BOTTOM PLANE TO
CONNECT PIN 8 GND TO THE
HIGH
PATH
PIN 17 EXPOSED PAD GND
NC
SW
NC
V
NC
BOOST
TCAP
GND
IN
ENHANCE THERMAL
SW
U
LT1977
CONDUCTIVITY
2
PGOOD
SHDN
SYNC
PGFB
BIAS
C
FB
V
SS
C
D1
W
L1
16
15
14
13
12
11
10
9
C5
C1
1977 F11
R3
R1
R2
C2
FROM BIAS TRACE
KEEP SEPARATE
KELVIN SENSE
LOAD
V
TRACE AND
U
FEEDBACK
OUT
1977 F12
implemented in the suggested layout of Figure 12. Short-
ening this path will also reduce the parasitic trace induc-
tance of approximately 25nH/inch. At switch off, this
parasitic inductance produces a flyback spike across the
LT1977 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT1977 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
The V
possible from the switch and boost nodes. The LT1977
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
Board layout also has a significant effect on thermal
resistance. Pin 8 and the exposed die pad, Pin 17, are a
continuous copper plate that runs under the LT1977 die.
This is the best thermal path for heat out of the package.
Reducing the thermal resistance from Pin 8 and exposed
pad onto the board will reduce die temperature and in-
crease the power capability of the LT1977. This is achieved
by providing as much copper area as possible around the
exposed pad. Adding multiple solder filled feedthroughs
under and around this pad to an internal ground plane will
also help. Similar treatment to the catch diode and coil
terminations will reduce any additional heating effects.
THERMAL CALCULATIONS
Power dissipation in the LT1977 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:
P
SW
C
and FB components should be kept as far away as
=
R
SW OUT
(
I
V
IN
) (
2
V
OUT
)
+
t
EFF
( ) (
1 2 /
I
OUT
)( )( )
V
IN
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