LTC1876EG#TR Linear Technology, LTC1876EG#TR Datasheet - Page 32

• Manufacturer Part Number: LTC1876EG#TR
• Description: IC CTRLR/REG STEP UP/DOWN 36SSOP
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck), Step-Up (Boost)r

Specifications of LTC1876EG#TR

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 3
• Voltage - Output: Adj to 34V
• Current - Output: 1A
• Frequency - Switching: 140kHz ~ 340kHz
• Voltage - Input: 3.5 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

LTC1876
APPLICATIO S I FOR ATIO
6. Are the SENSE
minimum PC trace spacing? The filter capacitor between
SENSE
IC.
7. Is the INTV
the IC, between the INTV
This capacitor carries the MOSFET drivers current peaks.
An additional 1 F ceramic capacitor placed immediately
next to the INTV
performance substantially.
8. Keep the switching nodes (SW1, SW2, AUXSW), top
gate nodes (TG1, TG2), and boost nodes (BOOST1,
BOOST2) away from sensitive small-signal nodes, espe-
cially from the opposites channel’s voltage and current
sensing feedback pins. All of these nodes have very large
and fast moving signals and therefore should be kept on
the “output side” of the LTC1876 and occupy minimum PC
trace area.
9. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one regulator on at a time. It is best to first start
with one of the step-down regulator and it is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the
operating voltage and current range expected in the
application. The frequency of operation should be main-
tained over the input voltage range down to dropout and
until the output load drops below the low current operation
threshold—typically 10% to 20% of the maximum de-
signed current level in Burst Mode operation.
32
+
and SENSE
CC
CC
decoupling capacitor connected close to
–
and SENSE
and PGND pins can help improve noise
U
–
should be as close as possible to the
CC
U
and the power ground pins?
+
leads routed together with
W
U
CC
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage
sensing inputs or inadequate loop compensation. Over-
compensation of the loop can be used to tame a poor PC
layout if regulator bandwidth optimization is not required.
Only after each controller is checked for their individual
performance should both controllers be turned on at the
same time. A particularly difficult region of operation is
when one controller channel is nearing its current com-
parator trip point when the other channel is turning on its
top MOSFET. This occurs around 50% duty cycle on either
channel due to the phasing of the internal clocks and may
cause minor duty cycle jitter.
Short-circuit testing can be performed to verify proper
overcurrent latchoff, or 5 A can be provided to the
RUN/SS pin(s) by resistors from V
ing upon the STBYMD pin programming), to prevent the
short-circuit latchoff from occurring.
Reduce V
regulator in dropout. Check the operation of the undervolt-
age lockout circuit by further lowering V
the outputs to verify operation.
Investigate whether any problems exist only at higher
output currents or only at higher input voltages. If prob-
lems coincide with high input voltages and low output
currents, look for capacitive coupling between the BOOST,
SW, TG, and possibly BG connections and the sensitive
voltage and current pins. The capacitor placed across the
current sensing pins needs to be placed immediately
adjacent to the pins of the IC. This capacitor helps to
minimize the effects of differential noise injection due to
high frequency capacitive coupling. If problems are en-
countered with high current output loading at lower input
voltages, look for inductive coupling between C
tky and the top MOSFET components to the sensitive
current and voltage sensing traces. In addition, investigate
common ground path voltage pickup between these com-
ponents and the SGND pin of the IC.
IN
from its nominal level to verify operation of the
IN
or INTV
IN
and monitoring
CC
IN
(depend-
, Schot-
1876fa