LM2744MTC/NOPB National Semiconductor, LM2744MTC/NOPB Datasheet - Page 15
![IC REG SYNC BUCK N-CH 14-TSSOP](/photos/6/62/66280/pkg_mtc14_sml.jpg)
LM2744MTC/NOPB
Manufacturer Part Number
LM2744MTC/NOPB
Description
IC REG SYNC BUCK N-CH 14-TSSOP
Manufacturer
National Semiconductor
Series
PowerWise®r
Type
Step-Down (Buck)r
Datasheet
1.LM2744MTCXNOPB.pdf
(24 pages)
Specifications of LM2744MTC/NOPB
Internal Switch(s)
No
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
0.5 ~ 1.5 V
Current - Output
20A
Frequency - Switching
50kHz ~ 1MHz
Voltage - Input
1 ~ 16 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
For Use With
LM2744EVAL - BOARD EVALUATION LM2744
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power - Output
-
Other names
*LM2744MTC
*LM2744MTC/NOPB
LM2744MTC
*LM2744MTC/NOPB
LM2744MTC
Losses in the high-side MOSFET can be broken down into
conduction loss, gate charging loss, and switching loss. Con-
duction, or I
In the above equations the factor 1.3 accounts for the in-
crease in MOSFET R
1.3 can be ignored and the R
using the R
datasheets.
Gate charging loss results from the current driving the gate
capacitance of the power MOSFETs, and is approximated as:
where ‘n’ is the number of MOSFETs (if multiple devices have
been placed in parallel), V
FET Gate Drivers section) and Q
MOSFET. If different types of MOSFETs are used, the ‘n’ term
can be ignored and their gate charges simply summed to form
a cumulative Q
and switching losses in that the actual dissipation occurs in
the LM2744, and not in the MOSFET itself.
Switching loss occurs during the brief transition period as the
high-side MOSFET turns on and off, during which both current
and voltage are present in the channel of the MOSFET. It can
be approximated as:
where t
Switching loss occurs in the high-side MOSFET only.
For this example, the maximum drain-to-source voltage ap-
plied to either MOSFET is 3.6V. The maximum drive voltage
at the gate of the high-side MOSFET is 3.1V, and the maxi-
mum drive voltage for the low-side MOSFET is 3.3V. Due to
the low drive voltages in this example, a MOSFET that turns
on fully with 3.1V of gate drive is needed. For designs of 5A
and under, dual MOSFETs in SO-8 provide a good tradeoff
between size, cost, and efficiency.
Support Components
C
as close as possible to the drain of the high-side MOSFET
and source of the low-side MOSFET (dual MOSFETs make
this easy). This capacitor should be X5R type dielectric or
better.
R
ensure smooth DC voltage for the chip supply. R
1-10Ω. C
C
R
drain power good signal (PWGD). The recommended value
is 10 kΩ connected to V
resistor can be omitted.
D
It allows for a minimum drop for both high and low-side
drivers. The MBR0520 or BAT54 work well in most designs.
R
calls for a peak current magnitude (I
a safe setting would be 6A. (This is below the saturation cur-
rent of the output inductor, which is 7A.) Following the equa-
tion from the Current Limit section, a 1.3kΩ resistor should be
used.
IN
CC
BOOT
PULL-UP
1
CS
- A small Schottky diode should be used for the bootstrap.
2 - A small (0.1 to 1 µF) ceramic capacitor should be placed
, C
- Resistor used to set the current limit. Since the design
- Bootstrap capacitor, typically 100nF.
CC
R
CC
- These are standard filter components designed to
and t
– This is a standard pull-up resistor for the open-
2
should be 1 µF, X5R type or better.
DSON
P
R loss, is approximately:
P
C
SW
F
G
= (1 - D) x (I
P
P
are the rise and fall times of the MOSFET.
. Gate charge loss differs from conduction
C
= 0.5 x V
Vs. Temperature curves in the MOSFET
GC
= D (I
(High-Side MOSFET)
(Low-Side MOSFET)
= n x (V
DSON
CC
O
. If this feature is not necessary, the
DD
2
IN
due to heating. Alternatively, the
x R
O
is the driving voltage (see MOS-
x I
DSON
DD
2
x R
DSON-HI
O
) x Q
GS
x (t
DSON-LO
of the MOSFET estimated
is the gate charge of the
G
r
OUT
+ t
x F
x 1.3)
f
+0.5*ΔI
) x F
SW
x 1.3)
SW
OUT
CC
should be
) of 4.8A,
15
R
the chip. The resistor value is calculated from equation in
Normal Operation section. For 300 kHz operation, a 97.6
kΩ resistor should be used.
C
ments and is calculated based on the equation given in the
section titled START UP/SOFT-START. Therefore, for a 7ms
delay, a 12nF capacitor is suitable.
Control Loop Compensation
The LM2744 uses voltage-mode (‘VM’) PWM control to cor-
rect changes in output voltage due to line and load transients.
One of the attractive advantages of voltage mode control is
its relative immunity to noise and layout. However VM re-
quires careful small signal compensation of the control loop
for achieving high bandwidth and good phase margin.
The control loop is comprised of two parts. The first is the
power stage, which consists of the duty cycle modulator, out-
put inductor, output capacitor, and load. The second part is
the error amplifier, which for the LM2744 is a 9MHz op-amp
used in the classic inverting configuration. Figure 11 shows
the regulator and control loop components.
One popular method for selecting the compensation compo-
nents is to create Bode plots of gain and phase for the power
stage and error amplifier. Combined, they make the overall
bandwidth and phase margin of the regulator easy to see.
Software tools such as Excel, MathCAD, and Matlab are use-
ful for showing how changes in compensation or the power
stage affect system gain and phase.
The power stage modulator provides a DC gain A
equal to the input voltage divided by the peak-to-peak value
of the PWM ramp. This ramp is 1.0VP-P for the LM2744. The
inductor and output capacitor create a double pole at fre-
quency f
single zero at frequency f
3.3V, these quantities are:
FADJ
SS
- The soft-start capacitor depends on the user require-
- This resistor is used to set the switching frequency of
DP
FIGURE 11. Power Stage and Error Amp
, and the capacitor ESR and capacitance create a
ESR
. For this example, with V
www.national.com
DC
20106064
that is
IN
=