MAX5951ETJ+ Maxim Integrated Products, MAX5951ETJ+ Datasheet - Page 15

• Manufacturer Part Number: MAX5951ETJ+
• Description: IC BUCK PWM CTRLR 12V/5V 32-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Step-Down (Buck)r

Specifications of MAX5951ETJ+

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 0.8 ~ 5.5 V
• Current - Output: 10A
• Frequency - Switching: 100kHz ~ 1MHz
• Voltage - Input: 8 ~ 16 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Power - Output: 2.76W
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Connect a resistive divider from OUT to FB to AGND to
set the output voltage. First, calculate the resistor from
OUT to FB using the guidelines in the Compensation
Design Guidelines section. Once R3 is known, calcu-
late R4 using the following equation:
where V
Three key inductor parameters must be specified for
operation with the MAX5951: inductance value (L), peak
inductor current (I
(I
operating frequency, input-to-output voltage differential,
and the peak-to-peak inductor current (∆I
∆I
tance value minimizes size and cost and improves large-
signal and transient response, but reduces efficiency
due to higher peak currents and higher peak-to-peak
output voltage ripple for the same output capacitor. A
higher inductance increases efficiency by reducing the
ripple current; however, resistive losses due to extra wire
turns can exceed the benefit gained from lower ripple
current levels especially when the inductance is
increased without also allowing for larger inductor
dimensions. A good rule of thumb is to choose ∆I
equal to 30% of the full-load current. Calculate the induc-
tor using the following equation:
V
optimum for typical conditions. The switching frequen-
cy is programmable between 100kHz and 1000kHz
(see the Oscillator/Synchronization Input (SYNCIN)/
Synchronization Output (SYNCOUT) section). The
peak-to-peak inductor current, which reflects the peak-
to-peak output ripple, is worst at the maximum input
voltage. See the output capacitor selection section to
verify that the worst-case output current ripple is
acceptable. The inductor saturation current (I
also important to avoid runaway current during continu-
ous output short-circuit conditions. Select an inductor
with an I
peak current.
SAT
IN
P-P
and V
). The minimum required inductance is a function of
allows for a lower inductor value. A lower induc-
FB
SAT
OUT
= 0.8V.
specification higher than the maximum
are typical values so that efficiency is
L
PEAK
______________________________________________________________________________________
=
R
Setting the Output Voltage
4
V
V
OUT IN
=
IN
), and inductor saturation current
⎡
⎢
⎣
×
V
(
V
f
OUT
V
SW
FB
R
3
−
×
Inductor Selection
−
12V/5V Input Buck PWM Controller
V
∆
1
OUT
I
⎤
⎥
⎦
P P
−
)
P-P
). Higher
SAT
) is
P-P
The discontinuous input current of the buck converter
causes large input ripple currents; therefore, the input
capacitor must be carefully chosen to withstand the
input ripple current and maintain the input voltage rip-
ple within design requirements. The total voltage ripple
is the sum of ∆V
and ∆V
which peaks at the end of the on cycle. Calculate the
input capacitance and ESR required for a specified rip-
ple using the following equations:
I
peak-to-peak inductor current, and f
frequency.
The MAX5951 includes UVLO hysteresis to avoid possi-
ble unintentional chattering during turn-on. Use addi-
tional bulk capacitance if the input source impedance is
high. When the input voltage is near the UVLO, addition-
al input capacitance helps avoid possible undershoot
below the UVLO threshold during transient loading.
The allowed output-voltage ripple and the maximum
deviation of the output voltage during load steps deter-
mine the required output capacitance and its ESR. The
output ripple is mainly composed of ∆V
the capacitor discharge) and ∆V
voltage drop across the ESR of the output capacitor).
The equations for calculating the peak-to-peak output-
voltage ripple are:
∆V
out of phase from each other. If using ceramic capaci-
tors, which generally have low ESR, ∆V
using electrolytic capacitors, ∆V
LOAD(MAX)
where
ESR
and ∆V
ESR
(caused by the ESR of the input capacitor),
is the maximum output current, ∆I
∆
ESR
C
Q
I
P P
IN
Q
−
∆
∆
are not directly additive since they are
=
V
V
=
(caused by the capacitor discharge)
Q
ESR
=
I
LOAD MAX
Output Capacitor Selection
⎛
⎜
⎝
=
I
(
LOAD MAX
Input Capacitor Selection
V
8
=
IN
×
ESR
∆
V
(
−
C
V
IN
(
V
∆
Q
OUT
∆
OUT
×
I
×
V
P P
×
)
ESR
f
−
SW
∆
×
)
ESR
×
f
I
+
SW
)
P P
⎛
⎜
⎝
2
×
f
−
V
SW
×
ESR
∆
OUT
V
V
L
dominates.
SW
I
IN
P P
OUT
2
−
(caused by the
is the switching
Q
⎞
⎟
⎠
⎞
⎟
⎠
Q
dominates. If
(caused by
P-P
is the
15